llvm.org GIT mirror llvm / 7bf2a57
[AMDGPU][MC] Fix for Bug 28211 + LIT tests - corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description) - address operand is not used - several opcodes have data operand - all opcodes have offset modifier - DS_AND_SRC2_B32: corrected typo in mnemo - DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32 - added CI/VI opcodes: - DS_CONDXCHG32_RTN_B64 - DS_GWS_SEMA_RELEASE_ALL - added VI opcodes: - DS_CONSUME - DS_APPEND - DS_ORDERED_COUNT Differential Revision: https://reviews.llvm.org/D31707 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299767 91177308-0d34-0410-b5e6-96231b3b80d8 Dmitry Preobrazhensky 2 years ago
7 changed file(s) with 221 addition(s) and 87 deletion(s). Raw diff Collapse all Expand all
202202 let has_data1 = 0;
203203 }
204204
205 class DS_1A_GDS : DS_Pseudo
206 (outs),
207 (ins VGPR_32:$addr),
208 "$addr gds"> {
209
210 let has_vdst = 0;
211 let has_data0 = 0;
212 let has_data1 = 0;
213 let has_offset = 0;
214 let has_offset0 = 0;
215 let has_offset1 = 0;
216
217 let has_gds = 0;
218 let gdsValue = 1;
205 class DS_GWS
206 : DS_Pseudo {
207
208 let has_vdst = 0;
209 let has_addr = 0;
210 let has_data0 = 0;
211 let has_data1 = 0;
212
213 let has_gds = 0;
214 let gdsValue = 1;
215 let AsmMatchConverter = "cvtDSGds";
216 }
217
218 class DS_GWS_0D
219 : DS_GWS
220 (ins offset:$offset, gds:$gds), "$offset gds">;
221
222 class DS_GWS_1D
223 : DS_GWS
224 (ins VGPR_32:$data0, offset:$offset, gds:$gds), "$data0$offset gds"> {
225
226 let has_data0 = 1;
219227 }
220228
221229 class DS_VOID : DS_Pseudo
389397 def DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>,
390398 AtomicNoRet<"ds_wrxchg2st64_b64", 1>;
391399
392 def DS_GWS_INIT : DS_1A_GDS<"ds_gws_init">;
393 def DS_GWS_SEMA_V : DS_1A_GDS<"ds_gws_sema_v">;
394 def DS_GWS_SEMA_BR : DS_1A_GDS<"ds_gws_sema_br">;
395 def DS_GWS_SEMA_P : DS_1A_GDS<"ds_gws_sema_p">;
396 def DS_GWS_BARRIER : DS_1A_GDS<"ds_gws_barrier">;
400 def DS_GWS_INIT : DS_GWS_1D<"ds_gws_init">;
401 def DS_GWS_SEMA_V : DS_GWS_0D<"ds_gws_sema_v">;
402 def DS_GWS_SEMA_BR : DS_GWS_1D<"ds_gws_sema_br">;
403 def DS_GWS_SEMA_P : DS_GWS_0D<"ds_gws_sema_p">;
404 def DS_GWS_BARRIER : DS_GWS_1D<"ds_gws_barrier">;
397405
398406 def DS_ADD_SRC2_U32 : DS_1A<"ds_add_src2_u32">;
399407 def DS_SUB_SRC2_U32 : DS_1A<"ds_sub_src2_u32">;
404412 def DS_MAX_SRC2_I32 : DS_1A<"ds_max_src2_i32">;
405413 def DS_MIN_SRC2_U32 : DS_1A<"ds_min_src2_u32">;
406414 def DS_MAX_SRC2_U32 : DS_1A<"ds_max_src2_u32">;
407 def DS_AND_SRC2_B32 : DS_1A<"ds_and_src_b32">;
415 def DS_AND_SRC2_B32 : DS_1A<"ds_and_src2_b32">;
408416 def DS_OR_SRC2_B32 : DS_1A<"ds_or_src2_b32">;
409417 def DS_XOR_SRC2_B32 : DS_1A<"ds_xor_src2_b32">;
410418 def DS_MIN_SRC2_F32 : DS_1A<"ds_min_src2_f32">;
447455 def DS_READ2ST64_B64 : DS_1A_Off8_RET<"ds_read2st64_b64", VReg_128>;
448456 }
449457
450 let SubtargetPredicate = isSICI in {
451458 def DS_CONSUME : DS_0A_RET<"ds_consume">;
452459 def DS_APPEND : DS_0A_RET<"ds_append">;
453460 def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
454 }
455461
456462 //===----------------------------------------------------------------------===//
457463 // Instruction definitions for CI and newer.
458464 //===----------------------------------------------------------------------===//
459 // Remaining instructions:
460 // DS_GWS_SEMA_RELEASE_ALL
461 // DS_WRAP_RTN_B32
462 // DS_CNDXCHG32_RTN_B64
463 // DS_CONDXCHG32_RTN_B128
464465
465466 let SubtargetPredicate = isCIVI in {
466467
467 def DS_WRAP_RTN_F32 : DS_1A1D_RET <"ds_wrap_rtn_f32">,
468 AtomicNoRet<"ds_wrap_f32", 1>;
468 def DS_WRAP_RTN_B32 : DS_1A2D_RET<"ds_wrap_rtn_b32">, AtomicNoRet<"", 1>;
469
470 def DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET<"ds_condxchg32_rtn_b64", VReg_64>,
471 AtomicNoRet<"", 1>;
472
473 def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
469474
470475 let mayStore = 0 in {
471476 def DS_READ_B96 : DS_1A_RET<"ds_read_b96", VReg_96>;
677682 def DS_MIN_RTN_F32_si : DS_Real_si<0x32, DS_MIN_RTN_F32>;
678683 def DS_MAX_RTN_F32_si : DS_Real_si<0x33, DS_MAX_RTN_F32>;
679684
680 // FIXME: this instruction is actually CI/VI
681 def DS_WRAP_RTN_F32_si : DS_Real_si<0x34, DS_WRAP_RTN_F32>;
685 // These instruction are CI/VI only
686 def DS_WRAP_RTN_B32_si : DS_Real_si<0x34, DS_WRAP_RTN_B32>;
687 def DS_CONDXCHG32_RTN_B64_si : DS_Real_si<0x7e, DS_CONDXCHG32_RTN_B64>;
688 def DS_GWS_SEMA_RELEASE_ALL_si : DS_Real_si<0x18, DS_GWS_SEMA_RELEASE_ALL>;
682689
683690 def DS_SWIZZLE_B32_si : DS_Real_si<0x35, DS_SWIZZLE_B32>;
684691 def DS_READ_B32_si : DS_Real_si<0x36, DS_READ_B32>;
819826 def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
820827 def DS_NOP_vi : DS_Real_vi<0x14, DS_NOP>;
821828 def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
822 def DS_GWS_INIT_vi : DS_Real_vi<0x19, DS_GWS_INIT>;
823 def DS_GWS_SEMA_V_vi : DS_Real_vi<0x1a, DS_GWS_SEMA_V>;
824 def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>;
825 def DS_GWS_SEMA_P_vi : DS_Real_vi<0x1c, DS_GWS_SEMA_P>;
826 def DS_GWS_BARRIER_vi : DS_Real_vi<0x1d, DS_GWS_BARRIER>;
829 def DS_GWS_INIT_vi : DS_Real_vi<0x99, DS_GWS_INIT>;
830 def DS_GWS_SEMA_V_vi : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
831 def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
832 def DS_GWS_SEMA_P_vi : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
833 def DS_GWS_BARRIER_vi : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
827834 def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
828835 def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
829836 def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
846853 def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
847854 def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
848855 def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
849 def DS_WRAP_RTN_F32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_F32>;
856 def DS_WRAP_RTN_B32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
850857 def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
851858 def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
852859 def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
855862 def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
856863 def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
857864 def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
865 def DS_CONSUME_vi : DS_Real_vi<0xbd, DS_CONSUME>;
866 def DS_APPEND_vi : DS_Real_vi<0xbe, DS_APPEND>;
867 def DS_ORDERED_COUNT_vi : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
858868 def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
859869 def DS_PERMUTE_B32_vi : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
860870 def DS_BPERMUTE_B32_vi : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
896906 def DS_WRXCHG_RTN_B64_vi : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
897907 def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
898908 def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
909 def DS_CONDXCHG32_RTN_B64_vi : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
910 def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
899911 def DS_CMPST_RTN_B64_vi : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
900912 def DS_CMPST_RTN_F64_vi : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
901913 def DS_MIN_RTN_F64_vi : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
112112 raw_ostream &O) {
113113 uint16_t Imm = MI->getOperand(OpNo).getImm();
114114 if (Imm != 0) {
115 O << " offset:";
115 O << ((OpNo == 0)? "offset:" : " offset:");
116116 printU16ImmDecOperand(MI, OpNo, O);
117117 }
118118 }
139139 // VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00]
140140
141141 ds_gws_init v2 gds
142 // SICI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x00,0x00,0x00]
143 // VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00]
144
145 ds_gws_sema_v v2 gds
146 // SICI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x00,0x00,0x00]
147 // VI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x35,0xd8,0x02,0x00,0x00,0x00]
142 // SICI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x66,0xd8,0x00,0x02,0x00,0x00]
143 // VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00]
144
145 ds_gws_init v3 offset:12345 gds
146 // SICI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x66,0xd8,0x00,0x03,0x00,0x00]
147 // VI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x33,0xd9,0x00,0x03,0x00,0x00]
148
149 ds_gws_sema_v gds
150 // SICI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
151 // VI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
152
153 ds_gws_sema_v offset:257 gds
154 // SICI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x6a,0xd8,0x00,0x00,0x00,0x00]
155 // VI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x35,0xd9,0x00,0x00,0x00,0x00]
148156
149157 ds_gws_sema_br v2 gds
150 // SICI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x00]
151 // VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd8,0x02,0x00,0x00,0x00]
152
153 ds_gws_sema_p v2 gds
154 // SICI: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x72,0xd8,0x02,0x00,0x00,0x00]
155 // VI: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x39,0xd8,0x02,0x00,0x00,0x00]
158 // SICI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x6e,0xd8,0x00,0x02,0x00,0x00]
159 // VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd9,0x00,0x02,0x00,0x00]
160
161 ds_gws_sema_p gds
162 // SICI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
163 // VI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
156164
157165 ds_gws_barrier v2 gds
158 // SICI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x76,0xd8,0x02,0x00,0x00,0x00]
159 // VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd8,0x02,0x00,0x00,0x00]
166 // SICI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x76,0xd8,0x00,0x02,0x00,0x00]
167 // VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd9,0x00,0x02,0x00,0x00]
160168
161169 ds_write_b8 v2, v4
162170 // SICI: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x04,0x00,0x00]
283291 // VI: ds_read_u16 v8, v2 ; encoding: [0x00,0x00,0x78,0xd8,0x02,0x00,0x00,0x08]
284292
285293
286 //ds_consume v8
287 // FIXMESICI: ds_consume v8 ; encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x08]
288 // FIXMEVI: ds_consume v8 ; encoding: [0x00,0x00,0x7a,0xd8,0x00,0x00,0x00,0x08]
289
290 //ds_append v8
291 // FIXMESICI: ds_append v8 ; encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x08]
292 // FIXMEVI: ds_append v8 ; encoding: [0x00,0x00,0x7c,0xd8,0x00,0x00,0x00,0x08]
293
294 //ds_ordered_count v8, v2 gds
295 // FIXMESICI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0xfe,0xd8,0x02,0x00,0x00,0x08]
296 // FIXMEVI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0x7f,0xd8,0x02,0x00,0x00,0x08]
294 ds_consume v8
295 // SICI: ds_consume v8 ; encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x08]
296 // VI: ds_consume v8 ; encoding: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x08]
297
298 ds_append v8
299 // SICI: ds_append v8 ; encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x08]
300 // VI: ds_append v8 ; encoding: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x08]
301
302 ds_ordered_count v8, v2 gds
303 // SICI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0xfe,0xd8,0x02,0x00,0x00,0x08]
304 // VI: ds_ordered_count v8, v2 gds ; encoding: [0x00,0x00,0x7f,0xd9,0x02,0x00,0x00,0x08]
297305
298306 ds_add_u64 v2, v[4:5]
299307 // SICI: ds_add_u64 v2, v[4:5] ; encoding: [0x00,0x00,0x00,0xd9,0x02,0x04,0x00,0x00]
1010
1111 // Use a token with the same name as a global
1212 ds_gws_init v2 gds
13 // VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00]
13 // VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00]
1414
1515 // Use a global with the same name as a token
1616 s_mov_b32 s0, gds
455455 // CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0x00]
456456
457457 ds_gws_init v1 gds
458 // CHECK: [0x00,0x00,0x66,0xd8,0x01,0x00,0x00,0x00]
459
460 ds_gws_sema_v v1 gds
461 // CHECK: [0x00,0x00,0x6a,0xd8,0x01,0x00,0x00,0x00]
458 // CHECK: [0x00,0x00,0x66,0xd8,0x00,0x01,0x00,0x00]
459
460 ds_gws_sema_v gds
461 // CHECK: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
462462
463463 ds_gws_sema_br v1 gds
464 // CHECK: [0x00,0x00,0x6e,0xd8,0x01,0x00,0x00,0x00]
465
466 ds_gws_sema_p v1 gds
467 // CHECK: [0x00,0x00,0x72,0xd8,0x01,0x00,0x00,0x00]
464 // CHECK: [0x00,0x00,0x6e,0xd8,0x00,0x01,0x00,0x00]
465
466 ds_gws_sema_p gds
467 // CHECK: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
468468
469469 ds_gws_barrier v1 gds
470 // CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x00]
470 // CHECK: [0x00,0x00,0x76,0xd8,0x00,0x01,0x00,0x00]
471
472 ds_gws_sema_release_all offset:65535 gds
473 // CHECK: [0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00]
474
475 ds_gws_sema_release_all gds
476 // CHECK: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
471477
472478 ds_write_b8 v1, v2 offset:65535
473479 // CHECK: [0xff,0xff,0x78,0xd8,0x01,0x02,0x00,0x00]
26592665 ds_max_src2_f64 v1 offset:65535 gds
26602666 // CHECK: [0xff,0xff,0x4e,0xdb,0x01,0x00,0x00,0x00]
26612667
2668 ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535
2669 // CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff]
2670
2671 ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535 gds
2672 // CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x03,0xff]
2673
2674 ds_wrap_rtn_b32 v255, v1, v2, v3
2675 // CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x03,0xff]
2676
2677 ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3]
2678 // CHECK: [0x00,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
2679
2680 ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] gds
2681 // CHECK: [0x00,0x00,0xfa,0xd9,0x01,0x02,0x00,0x05]
2682
2683 ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535
2684 // CHECK: [0xff,0xff,0xf8,0xd9,0x01,0xfe,0x00,0x05]
2685
26622686 exp mrt0, v0, v0, v0, v0
26632687 // CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
26642688
26772677 ds_max_src2_f64 v1 offset:65535 gds
26782678 // CHECK: [0xff,0xff,0xa7,0xd9,0x01,0x00,0x00,0x00]
26792679
2680 ds_and_src2_b32 v1
2681 // CHECK: [0x00,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
2682
2683 ds_and_src2_b32 v1 gds
2684 // CHECK: [0x00,0x00,0x13,0xd9,0x01,0x00,0x00,0x00]
2685
2686 ds_and_src2_b32 v255 offset:65535
2687 // CHECK: [0xff,0xff,0x12,0xd9,0xff,0x00,0x00,0x00]
2688
2689 ds_append v5
2690 // CHECK: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
2691
2692 ds_append v5 gds
2693 // CHECK: [0x00,0x00,0x7d,0xd9,0x00,0x00,0x00,0x05]
2694
2695 ds_append v255 offset:65535
2696 // CHECK: [0xff,0xff,0x7c,0xd9,0x00,0x00,0x00,0xff]
2697
2698 ds_consume v5
2699 // CHECK: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
2700
2701 ds_consume v5 gds
2702 // CHECK: [0x00,0x00,0x7b,0xd9,0x00,0x00,0x00,0x05]
2703
2704 ds_consume v255 offset:65535
2705 // CHECK: [0xff,0xff,0x7a,0xd9,0x00,0x00,0x00,0xff]
2706
2707 ds_ordered_count v5, v1 gds
2708 // CHECK: [0x00,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
2709
2710 ds_ordered_count v5, v255 offset:65535 gds
2711 // CHECK: [0xff,0xff,0x7f,0xd9,0xff,0x00,0x00,0x05]
2712
2713 ds_ordered_count v5, v255 gds
2714 // CHECK: [0x00,0x00,0x7f,0xd9,0xff,0x00,0x00,0x05]
2715
2716 ds_gws_barrier v1 gds
2717 // CHECK: [0x00,0x00,0x3b,0xd9,0x00,0x01,0x00,0x00]
2718
2719 ds_gws_barrier v255 offset:65535 gds
2720 // CHECK: [0xff,0xff,0x3b,0xd9,0x00,0xff,0x00,0x00]
2721
2722 ds_gws_init v1 gds
2723 // CHECK: [0x00,0x00,0x33,0xd9,0x00,0x01,0x00,0x00]
2724
2725 ds_gws_init v255 offset:65535 gds
2726 // CHECK: [0xff,0xff,0x33,0xd9,0x00,0xff,0x00,0x00]
2727
2728 ds_gws_sema_br v1 gds
2729 // CHECK: [0x00,0x00,0x37,0xd9,0x00,0x01,0x00,0x00]
2730
2731 ds_gws_sema_br v255 offset:65535 gds
2732 // CHECK: [0xff,0xff,0x37,0xd9,0x00,0xff,0x00,0x00]
2733
2734 ds_gws_sema_p offset:65535 gds
2735 // CHECK: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00]
2736
2737 ds_gws_sema_p gds
2738 // CHECK: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
2739
2740 ds_gws_sema_release_all offset:65535 gds
2741 // CHECK: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00]
2742
2743 ds_gws_sema_release_all gds
2744 // CHECK: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
2745
2746 ds_gws_sema_v offset:65535 gds
2747 // CHECK: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00]
2748
2749 ds_gws_sema_v gds
2750 // CHECK: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
2751
2752 ds_wrap_rtn_b32 v5, v255, v2, v3 gds
2753 // CHECK: [0x00,0x00,0x69,0xd8,0xff,0x02,0x03,0x05]
2754
2755 ds_wrap_rtn_b32 v5, v255, v2, v255 offset:65535
2756 // CHECK: [0xff,0xff,0x68,0xd8,0xff,0x02,0xff,0x05]
2757
2758 ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535 gds
2759 // CHECK: [0xff,0xff,0xfd,0xd8,0x01,0xfe,0x00,0x05]
2760
2761 ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255]
2762 // CHECK: [0x00,0x00,0xfc,0xd8,0x01,0xfe,0x00,0x05]
2763
26802764 exp mrt0, v0, v0, v0, v0
26812765 // CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
26822766
8080 # VI: ds_max_f32 v2, v4 ; encoding: [0x00,0x00,0x26,0xd8,0x02,0x04,0x00,0x00]
8181 0x00 0x00 0x26 0xd8 0x02 0x04 0x00 0x00
8282
83 # VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd8,0x02,0x00,0x00,0x00]
84 0x00 0x00 0x33 0xd8 0x02 0x00 0x00 0x00
85
86 # VI: ds_gws_sema_v v2 gds ; encoding: [0x00,0x00,0x35,0xd8,0x02,0x00,0x00,0x00]
87 0x00 0x00 0x35 0xd8 0x02 0x00 0x00 0x00
88
89 # VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd8,0x02,0x00,0x00,0x00]
90 0x00 0x00 0x37 0xd8 0x02 0x00 0x00 0x00
91
92 # VI: ds_gws_sema_p v2 gds ; encoding: [0x00,0x00,0x39,0xd8,0x02,0x00,0x00,0x00]
93 0x00 0x00 0x39 0xd8 0x02 0x00 0x00 0x00
94
95 # VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd8,0x02,0x00,0x00,0x00]
96 0x00 0x00 0x3b 0xd8 0x02 0x00 0x00 0x00
83 # VI: ds_gws_init v2 gds ; encoding: [0x00,0x00,0x33,0xd9,0x00,0x02,0x00,0x00]
84 0x00 0x00 0x33 0xd9 0x00 0x02 0x00,0x00
85
86 # VI: ds_gws_init v3 offset:12345 gds ; encoding: [0x39,0x30,0x33,0xd9,0x00,0x03,0x00,0x00]
87 0x39 0x30 0x33 0xd9 0x00 0x03 0x00 0x00
88
89 # VI: ds_gws_sema_v gds ; encoding: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
90 0x00 0x00 0x35 0xd9 0x00 0x00 0x00 0x00
91
92 # VI: ds_gws_sema_v offset:257 gds ; encoding: [0x01,0x01,0x35,0xd9,0x00,0x00,0x00,0x00]
93 0x01 0x01 0x35 0xd9 0x00 0x00 0x00 0x00
94
95 # VI: ds_gws_sema_br v2 gds ; encoding: [0x00,0x00,0x37,0xd9,0x00,0x02,0x00,0x00]
96 0x00 0x00 0x37 0xd9 0x00 0x02 0x00 0x00
97
98 # VI: ds_gws_sema_p gds ; encoding: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
99 0x00 0x00 0x39 0xd9 0x00 0x00 0x00 0x00
100
101 # VI: ds_gws_barrier v2 gds ; encoding: [0x00,0x00,0x3b,0xd9,0x00,0x02,0x00,0x00]
102 0x00 0x00 0x3b 0xd9 0x00 0x02 0x00 0x00
97103
98104 # VI: ds_write_b8 v2, v4 ; encoding: [0x00,0x00,0x3c,0xd8,0x02,0x04,0x00,0x00]
99105 0x00 0x00 0x3c 0xd8 0x02 0x04 0x00 0x00