llvm.org GIT mirror llvm / 7bf1c27
llvm bug #1350, parts 1, 2, and 3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36618 91177308-0d34-0410-b5e6-96231b3b80d8 Nate Begeman 13 years ago
6 changed file(s) with 133 addition(s) and 27 deletion(s). Raw diff Collapse all Expand all
7070 // immediately after the write. i.e. A register
7171 // that is defined but never used.
7272
73 /// offset - Offset to address of global or external, only valid for
74 /// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
75 int offset;
76
73 /// auxInfo - auxiliary information used by the MachineOperand
74 union {
75 /// offset - Offset to address of global or external, only valid for
76 /// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex
77 int offset;
78
79 /// subReg - SubRegister number, only valid for MO_Register. A value of 0
80 /// indicates the MO_Register has no subReg.
81 unsigned subReg;
82 } auxInfo;
83
7784 MachineOperand() {}
7885
7986 void print(std::ostream &os) const;
94101 Op.IsImp = false;
95102 Op.IsKill = false;
96103 Op.IsDead = false;
97 Op.offset = 0;
104 Op.auxInfo.offset = 0;
98105 return Op;
99106 }
100107
105112 IsKill = MO.IsKill;
106113 IsDead = MO.IsDead;
107114 opType = MO.opType;
108 offset = MO.offset;
115 auxInfo = MO.auxInfo;
109116 return *this;
110117 }
111118
168175 int getOffset() const {
169176 assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
170177 "Wrong MachineOperand accessor");
171 return offset;
178 return auxInfo.offset;
179 }
180 unsigned getSubReg() const {
181 assert(isRegister() && "Wrong MachineOperand accessor");
182 return auxInfo.subReg;
172183 }
173184 const char *getSymbolName() const {
174185 assert(isExternalSymbol() && "Wrong MachineOperand accessor");
253264 assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex() ||
254265 isJumpTableIndex()) &&
255266 "Wrong MachineOperand accessor");
256 offset = Offset;
267 auxInfo.offset = Offset;
268 }
269 void setSubReg(unsigned subReg) {
270 assert(isRegister() && "Wrong MachineOperand accessor");
271 auxInfo.subReg = subReg;
257272 }
258273 void setConstantPoolIndex(unsigned Idx) {
259274 assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
432447 Op.IsKill = IsKill;
433448 Op.IsDead = IsDead;
434449 Op.contents.RegNo = Reg;
435 Op.offset = 0;
450 Op.auxInfo.subReg = 0;
436451 }
437452
438453 /// addImmOperand - Add a zero extended constant argument to the
442457 MachineOperand &Op = AddNewOperand();
443458 Op.opType = MachineOperand::MO_Immediate;
444459 Op.contents.immedVal = Val;
445 Op.offset = 0;
460 Op.auxInfo.offset = 0;
446461 }
447462
448463 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
449464 MachineOperand &Op = AddNewOperand();
450465 Op.opType = MachineOperand::MO_MachineBasicBlock;
451466 Op.contents.MBB = MBB;
452 Op.offset = 0;
467 Op.auxInfo.offset = 0;
453468 }
454469
455470 /// addFrameIndexOperand - Add an abstract frame index to the instruction
458473 MachineOperand &Op = AddNewOperand();
459474 Op.opType = MachineOperand::MO_FrameIndex;
460475 Op.contents.immedVal = Idx;
461 Op.offset = 0;
476 Op.auxInfo.offset = 0;
462477 }
463478
464479 /// addConstantPoolndexOperand - Add a constant pool object index to the
468483 MachineOperand &Op = AddNewOperand();
469484 Op.opType = MachineOperand::MO_ConstantPoolIndex;
470485 Op.contents.immedVal = Idx;
471 Op.offset = Offset;
486 Op.auxInfo.offset = Offset;
472487 }
473488
474489 /// addJumpTableIndexOperand - Add a jump table object index to the
478493 MachineOperand &Op = AddNewOperand();
479494 Op.opType = MachineOperand::MO_JumpTableIndex;
480495 Op.contents.immedVal = Idx;
481 Op.offset = 0;
496 Op.auxInfo.offset = 0;
482497 }
483498
484499 void addGlobalAddressOperand(GlobalValue *GV, int Offset) {
485500 MachineOperand &Op = AddNewOperand();
486501 Op.opType = MachineOperand::MO_GlobalAddress;
487502 Op.contents.GV = GV;
488 Op.offset = Offset;
503 Op.auxInfo.offset = Offset;
489504 }
490505
491506 /// addExternalSymbolOperand - Add an external symbol operand to this instr
494509 MachineOperand &Op = AddNewOperand();
495510 Op.opType = MachineOperand::MO_ExternalSymbol;
496511 Op.contents.SymbolName = SymName;
497 Op.offset = 0;
512 Op.auxInfo.offset = 0;
498513 }
499514
500515 //===--------------------------------------------------------------------===//
4040 /// The SubRegs field is a zero terminated array of registers that are
4141 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
4242 /// The SuperRegs field is a zero terminated array of registers that are
43 /// super-registers of the specific register, e.g. RAX, EAX, are sub-registers
43 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
4444 /// of AX.
4545 ///
4646 struct TargetRegisterDesc {
353353 /// register scavenger to determine what registers are free.
354354 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
355355
356 /// getSubReg - Returns the physical register number of sub-register "Index"
357 /// for physical register RegNo.
358 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
359
356360 //===--------------------------------------------------------------------===//
357361 // Register Class Information
358362 //
3838 Op.IsKill = false;
3939 Op.IsDead = false;
4040 Op.contents.RegNo = *ImpDefs;
41 Op.offset = 0;
41 Op.auxInfo.subReg = 0;
4242 Operands.push_back(Op);
4343 }
4444 if (TID->ImplicitUses)
5050 Op.IsKill = false;
5151 Op.IsDead = false;
5252 Op.contents.RegNo = *ImpUses;
53 Op.offset = 0;
53 Op.auxInfo.subReg = 0;
5454 Operands.push_back(Op);
5555 }
5656 }
4242 }
4343
4444 // CR - One of the 8 4-bit condition registers
45 class CR5> num, string n> : PPCReg {
45 class CR3> num, string n> : PPCReg {
46 field bits<3> Num = num;
47 }
48
49 // CRBIT - One of the 32 1-bit condition register fields
50 class CRBIT num, string n> : PPCReg {
4651 field bits<5> Num = num;
4752 }
53
4854
4955 // General-purpose registers
5056 def R0 : GPR< 0, "r0">, DwarfRegNum<0>;
192198 def CR6 : CR<6, "cr6">, DwarfRegNum<74>;
193199 def CR7 : CR<7, "cr7">, DwarfRegNum<75>;
194200
201 // Condition register bits
202 def CR0LT : CRBIT< 0, "0">, DwarfRegNum<0>;
203 def CR0GT : CRBIT< 1, "1">, DwarfRegNum<0>;
204 def CR0EQ : CRBIT< 2, "2">, DwarfRegNum<0>;
205 def CR0UN : CRBIT< 3, "3">, DwarfRegNum<0>;
206 def CR1LT : CRBIT< 4, "4">, DwarfRegNum<0>;
207 def CR1GT : CRBIT< 5, "5">, DwarfRegNum<0>;
208 def CR1EQ : CRBIT< 6, "6">, DwarfRegNum<0>;
209 def CR1UN : CRBIT< 7, "7">, DwarfRegNum<0>;
210 def CR2LT : CRBIT< 8, "8">, DwarfRegNum<0>;
211 def CR2GT : CRBIT< 9, "9">, DwarfRegNum<0>;
212 def CR2EQ : CRBIT<10, "10">, DwarfRegNum<0>;
213 def CR2UN : CRBIT<11, "11">, DwarfRegNum<0>;
214 def CR3LT : CRBIT<12, "12">, DwarfRegNum<0>;
215 def CR3GT : CRBIT<13, "13">, DwarfRegNum<0>;
216 def CR3EQ : CRBIT<14, "14">, DwarfRegNum<0>;
217 def CR3UN : CRBIT<15, "15">, DwarfRegNum<0>;
218 def CR4LT : CRBIT<16, "16">, DwarfRegNum<0>;
219 def CR4GT : CRBIT<17, "17">, DwarfRegNum<0>;
220 def CR4EQ : CRBIT<18, "18">, DwarfRegNum<0>;
221 def CR4UN : CRBIT<19, "19">, DwarfRegNum<0>;
222 def CR5LT : CRBIT<20, "20">, DwarfRegNum<0>;
223 def CR5GT : CRBIT<21, "21">, DwarfRegNum<0>;
224 def CR5EQ : CRBIT<22, "22">, DwarfRegNum<0>;
225 def CR5UN : CRBIT<23, "23">, DwarfRegNum<0>;
226 def CR6LT : CRBIT<24, "24">, DwarfRegNum<0>;
227 def CR6GT : CRBIT<25, "25">, DwarfRegNum<0>;
228 def CR6EQ : CRBIT<26, "26">, DwarfRegNum<0>;
229 def CR6UN : CRBIT<27, "27">, DwarfRegNum<0>;
230 def CR7LT : CRBIT<28, "28">, DwarfRegNum<0>;
231 def CR7GT : CRBIT<29, "29">, DwarfRegNum<0>;
232 def CR7EQ : CRBIT<30, "30">, DwarfRegNum<0>;
233 def CR7UN : CRBIT<31, "31">, DwarfRegNum<0>;
234
235 def : SubRegSet<1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
236 [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>;
237 def : SubRegSet<2, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
238 [CR0GT, CR1GT, CR2GT, CR3GT, CR4GT, CR5GT, CR6GT, CR7GT]>;
239 def : SubRegSet<3, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
240 [CR0EQ, CR1EQ, CR2EQ, CR3EQ, CR4EQ, CR5EQ, CR6EQ, CR7EQ]>;
241 def : SubRegSet<4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
242 [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN]>;
243
195244 // Link register
196245 def LR : SPR<8, "lr">, DwarfRegNum<65>;
197246 //let Aliases = [LR] in
6666 let SubRegs = subregs;
6767 }
6868
69 // RegisterGroup - This can be used to define instances of Register which
70 // need to specify aliases.
71 // List "aliases" specifies which registers are aliased to this one. This
72 // allows the code generator to be careful not to put two values with
73 // overlapping live ranges into registers which alias.
74 class RegisterGroup aliases> : Register {
75 let Aliases = aliases;
69 // SubRegSet - This can be used to define a specific mapping of registers to
70 // indices, for use as named subregs of a particular physical register. Each
71 // register in 'subregs' becomes an addressable subregister at index 'n' of the
72 // corresponding register in 'regs'.
73 class SubRegSet regs, list subregs> {
74 int index = n;
75
76 list From = regs;
77 list To = subregs;
7678 }
7779
7880 // RegisterClass - Now that all of the registers are defined, and aliases
6060 << " " << ClassName
6161 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
6262 << " int getDwarfRegNum(unsigned RegNum) const;\n"
63 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
6364 << "};\n\n";
6465
6566 const std::vector &RegisterClasses =
321322 std::map > RegisterSubRegs;
322323 std::map > RegisterSuperRegs;
323324 std::map > RegisterAliases;
325 std::map > > SubRegVectors;
324326 const std::vector &Regs = Target.getRegisters();
325327
326328 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
440442
441443 std::string ClassName = Target.getName() + "GenRegisterInfo";
442444
445 // Calculate the mapping of subregister+index pairs to physical registers.
446 std::vector SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
447 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
448 int subRegIndex = SubRegs[i]->getValueAsInt("index");
449 std::vector From = SubRegs[i]->getValueAsListOfDefs("From");
450 std::vector To = SubRegs[i]->getValueAsListOfDefs("To");
451
452 assert((From.size() == To.size()) &&
453 "SubRegSet has mismatched from/to size");
454
455 // For each entry in from/to vectors, insert the to register at index
456 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
457 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
458 }
459
460 // Emit the subregister + index mapping function based on the information
461 // calculated above.
462 OS << "unsigned " << ClassName
463 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
464 << " switch (RegNo) {\n"
465 << " default: abort(); break;\n";
466 for (std::map > >::iterator
467 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
468 OS << " case " << getQualifiedName(I->first) << ":\n";
469 OS << " switch (Index) {\n";
470 OS << " default: abort(); break;\n";
471 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
472 OS << " case " << (I->second)[i].first << ": return "
473 << getQualifiedName((I->second)[i].second) << ";\n";
474 OS << " }; break;\n";
475 }
476 OS << " };\n";
477 OS << "}\n\n";
478
443479 // Emit the constructor of the class...
444480 OS << ClassName << "::" << ClassName
445481 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"