llvm.org GIT mirror llvm / 7bc59bc
added a skeleton of the ARM backend git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 13 years ago
16 changed file(s) with 901 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
284284 [Build specific host targets: all,host-only,{target-name} (default=all)]),,
285285 enableval=all)
286286 case "$enableval" in
287 all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64" ;;
287 all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM" ;;
288288 host-only)
289289 case "$llvm_cv_target_arch" in
290290 x86) TARGETS_TO_BUILD="X86" ;;
31063106 enableval=all
31073107 fi;
31083108 case "$enableval" in
3109 all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64" ;;
3109 all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM" ;;
31103110 host-only)
31113111 case "$llvm_cv_target_arch" in
31123112 x86) TARGETS_TO_BUILD="X86" ;;
0 //===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the "Instituto Nokia de Tecnologia" and
5 // is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the entry points for global functions defined in the LLVM
11 // ARM back-end.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #ifndef TARGET_ARM_H
16 #define TARGET_ARM_H
17
18 #include
19 #include
20
21 namespace llvm {
22 class FunctionPass;
23 class TargetMachine;
24
25 FunctionPass *createARMISelDag(TargetMachine &TM);
26 FunctionPass *createARMCodePrinterPass(std::ostream &OS, TargetMachine &TM);
27 } // end namespace llvm;
28
29 // Defines symbolic names for ARM registers. This defines a mapping from
30 // register name to register number.
31 //
32 #include "ARMGenRegisterNames.inc"
33
34 // Defines symbolic names for the ARM instructions.
35 //
36 #include "ARMGenInstrNames.inc"
37
38
39 #endif
0 //===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the "Instituto Nokia de Tecnologia" and
5 // is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
16
17 include "../Target.td"
18
19 //===----------------------------------------------------------------------===//
20 // Register File Description
21 //===----------------------------------------------------------------------===//
22
23 include "ARMRegisterInfo.td"
24
25 //===----------------------------------------------------------------------===//
26 // Instruction Descriptions
27 //===----------------------------------------------------------------------===//
28
29 include "ARMInstrInfo.td"
30
31 def ARMInstrInfo : InstrInfo {
32 // Define how we want to layout our target-specific information field.
33 let TSFlagsFields = [];
34 let TSFlagsShifts = [];
35 }
36
37 //===----------------------------------------------------------------------===//
38 // Declare the target which we are implementing
39 //===----------------------------------------------------------------------===//
40
41 def ARM : Target {
42 // Pointers are 32-bits in size.
43 let PointerType = i32;
44
45 // FIXME: Specify callee-saved registers
46 let CalleeSavedRegisters = [];
47
48 // Pull in Instruction Info:
49 let InstructionSet = ARMInstrInfo;
50 }
0 //===-- ARMAsmPrinter.cpp - ARM LLVM assembly writer ----------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the "Instituto Nokia de Tecnologia" and
5 // is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "ARM.h"
16 #include "ARMInstrInfo.h"
17 #include "llvm/Constants.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/Module.h"
20 #include "llvm/Assembly/Writer.h"
21 #include "llvm/CodeGen/AsmPrinter.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Support/Mangler.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/ADT/StringExtras.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/MathExtras.h"
31 #include
32 #include
33 using namespace llvm;
34
35 namespace {
36 Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
37
38 struct ARMAsmPrinter : public AsmPrinter {
39 ARMAsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) {
40 Data16bitsDirective = "\t.half\t";
41 Data32bitsDirective = "\t.word\t";
42 Data64bitsDirective = 0;
43 ZeroDirective = "\t.skip\t";
44 CommentString = "!";
45 ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
46 }
47
48 /// We name each basic block in a Function with a unique number, so
49 /// that we can consistently refer to them later. This is cleared
50 /// at the beginning of each call to runOnMachineFunction().
51 ///
52 typedef std::map ValueMapTy;
53 ValueMapTy NumberForBB;
54
55 virtual const char *getPassName() const {
56 return "ARM Assembly Printer";
57 }
58
59 void printOperand(const MachineInstr *MI, int opNum);
60 void printMemOperand(const MachineInstr *MI, int opNum,
61 const char *Modifier = 0);
62 void printCCOperand(const MachineInstr *MI, int opNum);
63
64 bool printInstruction(const MachineInstr *MI); // autogenerated.
65 bool runOnMachineFunction(MachineFunction &F);
66 bool doInitialization(Module &M);
67 bool doFinalization(Module &M);
68 };
69 } // end of anonymous namespace
70
71 #include "ARMGenAsmWriter.inc"
72
73 /// createARMCodePrinterPass - Returns a pass that prints the ARM
74 /// assembly code for a MachineFunction to the given output stream,
75 /// using the given target machine description. This should work
76 /// regardless of whether the function is in SSA form.
77 ///
78 FunctionPass *llvm::createARMCodePrinterPass(std::ostream &o,
79 TargetMachine &tm) {
80 return new ARMAsmPrinter(o, tm);
81 }
82
83 /// runOnMachineFunction - This uses the printMachineInstruction()
84 /// method to print assembly for each instruction.
85 ///
86 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
87 assert(0 && "not implemented");
88 // We didn't modify anything.
89 return false;
90 }
91
92 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
93 assert(0 && "not implemented");
94 }
95
96 void ARMAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
97 const char *Modifier) {
98 assert(0 && "not implemented");
99 }
100
101 void ARMAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) {
102 assert(0 && "not implemented");
103 }
104
105 bool ARMAsmPrinter::doInitialization(Module &M) {
106 Mang = new Mangler(M);
107 return false; // success
108 }
109
110 bool ARMAsmPrinter::doFinalization(Module &M) {
111 assert(0 && "not implemented");
112 AsmPrinter::doFinalization(M);
113 return false; // success
114 }
0 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by Chris Lattner and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines an instruction selector for the ARM target.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "ARM.h"
14 #include "ARMTargetMachine.h"
15 #include "llvm/DerivedTypes.h"
16 #include "llvm/Function.h"
17 #include "llvm/Intrinsics.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Support/Debug.h"
26 #include
27 #include
28 using namespace llvm;
29
30 namespace ARMISD {
31 enum {
32 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
33 RET_FLAG,
34 };
35 }
36
37 namespace {
38 class ARMTargetLowering : public TargetLowering {
39 public:
40 ARMTargetLowering(TargetMachine &TM);
41 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
42
43 virtual std::pair
44 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
45 unsigned CC,
46 bool isTailCall, SDOperand Callee, ArgListTy &Args,
47 SelectionDAG &DAG);
48
49 };
50
51 }
52
53 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
54 : TargetLowering(TM) {
55 setOperationAction(ISD::RET, MVT::Other, Custom);
56 }
57
58 std::pair
59 ARMTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
60 bool isVarArg, unsigned CC,
61 bool isTailCall, SDOperand Callee,
62 ArgListTy &Args, SelectionDAG &DAG) {
63 assert(0 && "Not implemented");
64 }
65
66 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
67 SDOperand Copy;
68 switch(Op.getNumOperands()) {
69 default:
70 assert(0 && "Do not know how to return this many arguments!");
71 abort();
72 case 1:
73 return SDOperand(); // ret void is legal
74 case 2:
75 Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
76 break;
77 }
78
79 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
80 }
81
82 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
83 switch (Op.getOpcode()) {
84 default:
85 assert(0 && "Should not custom lower this!");
86 case ISD::RET:
87 return LowerRET(Op, DAG);
88 }
89 }
90
91 //===----------------------------------------------------------------------===//
92 // Instruction Selector Implementation
93 //===----------------------------------------------------------------------===//
94
95 //===--------------------------------------------------------------------===//
96 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
97 /// instructions for SelectionDAG operations.
98 ///
99 namespace {
100 class ARMDAGToDAGISel : public SelectionDAGISel {
101 ARMTargetLowering Lowering;
102
103 public:
104 ARMDAGToDAGISel(TargetMachine &TM)
105 : SelectionDAGISel(Lowering), Lowering(TM) {
106 }
107
108 void Select(SDOperand &Result, SDOperand Op);
109 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
110
111 // Include the pieces autogenerated from the target description.
112 #include "ARMGenDAGISel.inc"
113 };
114
115 void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
116 DEBUG(BB->dump());
117
118 DAG.setRoot(SelectRoot(DAG.getRoot()));
119 CodeGenMap.clear();
120 DAG.RemoveDeadNodes();
121
122 ScheduleAndEmitDAG(DAG);
123 }
124
125 void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
126 SelectCode(Result, Op);
127 }
128
129 } // end anonymous namespace
130
131 /// createARMISelDag - This pass converts a legalized DAG into a
132 /// ARM-specific DAG, ready for instruction scheduling.
133 ///
134 FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
135 return new ARMDAGToDAGISel(TM);
136 }
0 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the "Instituto Nokia de Tecnologia" and
5 // is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "ARMInstrInfo.h"
15 #include "ARM.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "ARMGenInstrInfo.inc"
18 using namespace llvm;
19
20 ARMInstrInfo::ARMInstrInfo()
21 : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
22 }
23
24 /// Return true if the instruction is a register to register move and
25 /// leave the source and dest operands in the passed parameters.
26 ///
27 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
28 unsigned &SrcReg, unsigned &DstReg) const {
29 // We look for 3 kinds of patterns here:
30 // or with G0 or 0
31 // add with G0 or 0
32 // fmovs or FpMOVD (pseudo double move).
33 assert(0 && "not implemented");
34 return false;
35 }
36
37 /// isLoadFromStackSlot - If the specified machine instruction is a direct
38 /// load from a stack slot, return the virtual or physical register number of
39 /// the destination along with the FrameIndex of the loaded stack slot. If
40 /// not, return 0. This predicate must return 0 if the instruction has
41 /// any side effects other than loading from the stack slot.
42 unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
43 int &FrameIndex) const {
44 assert(0 && "not implemented");
45 return 0;
46 }
47
48 /// isStoreToStackSlot - If the specified machine instruction is a direct
49 /// store to a stack slot, return the virtual or physical register number of
50 /// the source reg along with the FrameIndex of the loaded stack slot. If
51 /// not, return 0. This predicate must return 0 if the instruction has
52 /// any side effects other than storing to the stack slot.
53 unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI,
54 int &FrameIndex) const {
55 assert(0 && "not implemented");
56 return 0;
57 }
0 //===- ARMInstrInfo.h - ARM Instruction Information --------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the "Instituto Nokia de Tecnologia" and
5 // is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef ARMINSTRUCTIONINFO_H
15 #define ARMINSTRUCTIONINFO_H
16
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "ARMRegisterInfo.h"
19
20 namespace llvm {
21
22 class ARMInstrInfo : public TargetInstrInfo {
23 const ARMRegisterInfo RI;
24 public:
25 ARMInstrInfo();
26
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
30 ///
31 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
32
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
35 ///
36 virtual bool isMoveInstr(const MachineInstr &MI,
37 unsigned &SrcReg, unsigned &DstReg) const;
38
39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
40 /// load from a stack slot, return the virtual or physical register number of
41 /// the destination along with the FrameIndex of the loaded stack slot. If
42 /// not, return 0. This predicate must return 0 if the instruction has
43 /// any side effects other than loading from the stack slot.
44 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
45
46 /// isStoreToStackSlot - If the specified machine instruction is a direct
47 /// store to a stack slot, return the virtual or physical register number of
48 /// the source reg along with the FrameIndex of the loaded stack slot. If
49 /// not, return 0. This predicate must return 0 if the instruction has
50 /// any side effects other than storing to the stack slot.
51 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
52 };
53
54 }
55
56 #endif
0 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the "Instituto Nokia de Tecnologia" and
5 // is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the ARM instructions in TableGen format.
11 //
12 //===----------------------------------------------------------------------===//
13
14
15
16 //===----------------------------------------------------------------------===//
17 // Instructions
18 //===----------------------------------------------------------------------===//
19
20 class InstARM pattern> : Instruction {
21 let Namespace = "ARM";
22
23 dag OperandList = ops;
24 let AsmString = asmstr;
25 let Pattern = pattern;
26 }
27
28 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
29 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, [SDNPHasChain]>;
30 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, [SDNPHasChain]>;
31
32 def SDT_ARMRetFlag : SDTypeProfile<0, 0, []>;
33 def retflag : SDNode<"ARMISD::RET_FLAG", SDT_ARMRetFlag,
34 [SDNPHasChain, SDNPOptInFlag]>;
35
36 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
37 "!ADJCALLSTACKUP $amt",
38 [(callseq_end imm:$amt)]>;
39
40 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
41 "!ADJCALLSTACKDOWN $amt",
42 [(callseq_start imm:$amt)]>;
43
44 def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
45 "ldr $dst, [$addr]",
46 [(set IntRegs:$dst, (load IntRegs:$addr))]>;
47
48 def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
49 "str $src, [$addr]",
50 [(store IntRegs:$src, IntRegs:$addr)]>;
51
52 def mov : InstARM<(ops IntRegs:$dst, IntRegs:$b),
53 "mov $dst, $b", []>;
0 //===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the "Instituto Nokia de Tecnologia" and
5 // is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the ARM implementation of the MRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "ARM.h"
15 #include "ARMRegisterInfo.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineLocation.h"
20 #include "llvm/Type.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include
23 using namespace llvm;
24
25 ARMRegisterInfo::ARMRegisterInfo()
26 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
27 }
28
29 void ARMRegisterInfo::
30 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
31 unsigned SrcReg, int FI,
32 const TargetRegisterClass *RC) const {
33 // On the order of operands here: think "[FI + 0] = SrcReg".
34 assert (RC == ARM::IntRegsRegisterClass);
35 BuildMI(MBB, I, ARM::str, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
36 }
37
38 void ARMRegisterInfo::
39 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
40 unsigned DestReg, int FI,
41 const TargetRegisterClass *RC) const {
42 assert (RC == ARM::IntRegsRegisterClass);
43 BuildMI(MBB, I, ARM::ldr, 2, DestReg).addFrameIndex(FI).addImm(0);
44 }
45
46 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator I,
48 unsigned DestReg, unsigned SrcReg,
49 const TargetRegisterClass *RC) const {
50 assert (RC == ARM::IntRegsRegisterClass);
51 BuildMI(MBB, I, ARM::mov, 1, DestReg).addReg(SrcReg);
52 }
53
54 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
55 unsigned OpNum,
56 int FI) const {
57 return NULL;
58 }
59
60 void ARMRegisterInfo::
61 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator I) const {
63 MBB.erase(I);
64 }
65
66 void
67 ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
68 assert(0 && "Not Implemented");
69 }
70
71 void ARMRegisterInfo::
72 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
73
74 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
75 }
76
77 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
78 MachineBasicBlock &MBB) const {
79 }
80
81 unsigned ARMRegisterInfo::getRARegister() const {
82 return ARM::R14;
83 }
84
85 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
86 return ARM::R13;
87 }
88
89 #include "ARMGenRegisterInfo.inc"
90
0 //===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the "Instituto Nokia de Tecnologia" and
5 // is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the ARM implementation of the MRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef ARMREGISTERINFO_H
15 #define ARMREGISTERINFO_H
16
17 #include "llvm/Target/MRegisterInfo.h"
18 #include "ARMGenRegisterInfo.h.inc"
19
20 namespace llvm {
21
22 class Type;
23
24 struct ARMRegisterInfo : public ARMGenRegisterInfo {
25
26 ARMRegisterInfo();
27
28 /// Code Generation virtual methods...
29 void storeRegToStackSlot(MachineBasicBlock &MBB,
30 MachineBasicBlock::iterator MBBI,
31 unsigned SrcReg, int FrameIndex,
32 const TargetRegisterClass *RC) const;
33
34 void loadRegFromStackSlot(MachineBasicBlock &MBB,
35 MachineBasicBlock::iterator MBBI,
36 unsigned DestReg, int FrameIndex,
37 const TargetRegisterClass *RC) const;
38
39 void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
40 unsigned DestReg, unsigned SrcReg,
41 const TargetRegisterClass *RC) const;
42
43 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
44 unsigned OpNum,
45 int FrameIndex) const;
46
47 void eliminateCallFramePseudoInstr(MachineFunction &MF,
48 MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator I) const;
50
51 void eliminateFrameIndex(MachineBasicBlock::iterator II) const;
52
53 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
54
55 void emitPrologue(MachineFunction &MF) const;
56 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
57
58 // Debug information queries.
59 unsigned getRARegister() const;
60 unsigned getFrameRegister(MachineFunction &MF) const;
61 };
62
63 } // end namespace llvm
64
65 #endif
0 //===- ARMRegisterInfo.td - ARM Register defs ----------*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the "Instituto Nokia de Tecnologia" and
5 // is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the ARM register file
12 //===----------------------------------------------------------------------===//
13
14 // Registers are identified with 4-bit ID numbers.
15 class ARMReg num, string n> : Register {
16 field bits<4> Num;
17 let Namespace = "ARM";
18 }
19
20 // Integer registers
21 def R0 : ARMReg< 0, "R0">, DwarfRegNum<0>;
22 def R1 : ARMReg< 1, "R1">, DwarfRegNum<1>;
23 def R2 : ARMReg< 2, "R2">, DwarfRegNum<2>;
24 def R3 : ARMReg< 3, "R3">, DwarfRegNum<3>;
25 def R4 : ARMReg< 4, "R4">, DwarfRegNum<4>;
26 def R5 : ARMReg< 5, "R5">, DwarfRegNum<5>;
27 def R6 : ARMReg< 6, "R6">, DwarfRegNum<6>;
28 def R7 : ARMReg< 7, "R7">, DwarfRegNum<7>;
29 def R8 : ARMReg< 8, "R8">, DwarfRegNum<8>;
30 def R9 : ARMReg< 9, "R9">, DwarfRegNum<9>;
31 def R10 : ARMReg<10, "R10">, DwarfRegNum<10>;
32 def R11 : ARMReg<11, "R11">, DwarfRegNum<11>;
33 def R12 : ARMReg<12, "R12">, DwarfRegNum<12>;
34 def R13 : ARMReg<13, "R13">, DwarfRegNum<13>;
35 def R14 : ARMReg<14, "R14">, DwarfRegNum<14>;
36 def R15 : ARMReg<15, "R15">, DwarfRegNum<15>;
37
38 // Register classes.
39 //
40 // FIXME: the register order should be defined in terms of the preferred
41 // allocation order...
42 //
43 def IntRegs : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
44 R7, R8, R9, R10, R11, R12,
45 R13, R14, R15]> {
46 let MethodProtos = [{
47 iterator allocation_order_end(MachineFunction &MF) const;
48 }];
49 let MethodBodies = [{
50 IntRegsClass::iterator
51 IntRegsClass::allocation_order_end(MachineFunction &MF) const {
52 return end() - 1;
53 }
54 }];
55 }
0 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the "Instituto Nokia de Tecnologia" and
5 // is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "ARMTargetMachine.h"
14 #include "ARM.h"
15 #include "llvm/Assembly/PrintModulePass.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Target/TargetMachineRegistry.h"
22 #include "llvm/Transforms/Scalar.h"
23 #include
24 using namespace llvm;
25
26 namespace {
27 // Register the target.
28 RegisterTarget X("arm", " ARM");
29 }
30
31 /// TargetMachine ctor - Create an ILP32 architecture model
32 ///
33 ARMTargetMachine::ARMTargetMachine(const Module &M, const std::string &FS)
34 : TargetMachine("ARM"),
35 DataLayout("ARM", false, 4, 4),
36 InstrInfo(),
37 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
38 }
39
40 unsigned ARMTargetMachine::getModuleMatchQuality(const Module &M) {
41 std::string TT = M.getTargetTriple();
42 if (TT.size() >= 4 && std::string(TT.begin(), TT.begin()+4) == "arm-")
43 return 20;
44
45 if (M.getPointerSize() == Module::Pointer32)
46 return 1;
47 else
48 return 0;
49 }
50
51 /// addPassesToEmitFile - Add passes to the specified pass manager
52 /// to implement a static compiler for this target.
53 ///
54 bool ARMTargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
55 CodeGenFileType FileType,
56 bool Fast) {
57 if (FileType != TargetMachine::AssemblyFile)
58 return true;
59
60 // Run loop strength reduction before anything else.
61 if (!Fast)
62 PM.add(createLoopStrengthReducePass());
63
64 // FIXME: Implement efficient support for garbage collection intrinsics.
65 PM.add(createLowerGCPass());
66
67 // FIXME: implement the invoke/unwind instructions!
68 PM.add(createLowerInvokePass());
69
70 // Print LLVM code input to instruction selector:
71 if (PrintMachineCode)
72 PM.add(new PrintFunctionPass());
73
74 // Make sure that no unreachable blocks are instruction selected.
75 PM.add(createUnreachableBlockEliminationPass());
76
77 PM.add(createARMISelDag(*this));
78
79 // Print machine instructions as they were initially generated.
80 if (PrintMachineCode)
81 PM.add(createMachineFunctionPrinterPass(&std::cerr));
82
83 PM.add(createRegisterAllocator());
84 PM.add(createPrologEpilogCodeInserter());
85
86 // Print machine instructions after register allocation and prolog/epilog
87 // insertion.
88 if (PrintMachineCode)
89 PM.add(createMachineFunctionPrinterPass(&std::cerr));
90
91 // Output assembly language.
92 PM.add(createARMCodePrinterPass(Out, *this));
93
94 // Delete the MachineInstrs we generated, since they're no longer needed.
95 PM.add(createMachineCodeDeleter());
96 return false;
97 }
98
0 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by the "Instituto Nokia de Tecnologia" and
5 // is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the ARM specific subclass of TargetMachine.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
16
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetFrameInfo.h"
20 #include "llvm/PassManager.h"
21 #include "ARMInstrInfo.h"
22
23 namespace llvm {
24
25 class Module;
26
27 class ARMTargetMachine : public TargetMachine {
28 const TargetData DataLayout; // Calculates type size & alignment
29 ARMInstrInfo InstrInfo;
30 TargetFrameInfo FrameInfo;
31 public:
32 ARMTargetMachine(const Module &M, const std::string &FS);
33
34 virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
35 virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
36 virtual const MRegisterInfo *getRegisterInfo() const {
37 return &InstrInfo.getRegisterInfo();
38 }
39 virtual const TargetData *getTargetData() const { return &DataLayout; }
40 static unsigned getModuleMatchQuality(const Module &M);
41
42 virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out,
43 CodeGenFileType FileType, bool Fast);
44 };
45
46 } // end namespace llvm
47
48 #endif
0 ##===- lib/Target/ARM/Makefile -----------------------------*- Makefile -*-===##
1 #
2 # The LLVM Compiler Infrastructure
3 #
4 # This file was developed by the "Instituto Nokia de Tecnologia" and
5 # is distributed under the University of Illinois Open Source
6 # License. See LICENSE.TXT for details.
7 #
8 ##===----------------------------------------------------------------------===##
9 LEVEL = ../../..
10 LIBRARYNAME = LLVMARM
11 TARGET = ARM
12
13 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \
15 ARMGenRegisterInfo.inc ARMGenInstrNames.inc \
16 ARMGenInstrInfo.inc ARMGenAsmWriter.inc \
17 ARMGenDAGISel.inc
18
19 include $(LEVEL)/Makefile.common
20
4747 USEDLIBS += LLVMIA64
4848 endif
4949
50 #Check for ARM Target
51 ifneq ($(strip $(filter ARM,$(TARGETS_TO_BUILD))),)
52 USEDLIBS += LLVMARM
53 endif
54
5055 USEDLIBS += \
5156 LLVMSelectionDAG \
5257 LLVMCodeGen \