llvm.org GIT mirror llvm / 7b78e6e
TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFC Differential Revision: https://reviews.llvm.org/D22925 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276997 91177308-0d34-0410-b5e6-96231b3b80d8 Sjoerd Meijer 3 years ago
23 changed file(s) with 50 addition(s) and 50 deletion(s). Raw diff Collapse all Expand all
176176 void AArch64BranchRelaxation::computeBlockSize(const MachineBasicBlock &MBB) {
177177 unsigned Size = 0;
178178 for (const MachineInstr &MI : MBB)
179 Size += TII->GetInstSizeInBytes(MI);
179 Size += TII->getInstSizeInBytes(MI);
180180 BlockInfo[MBB.getNumber()].Size = Size;
181181 }
182182
194194 // Sum instructions before MI in MBB.
195195 for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
196196 assert(I != MBB->end() && "Didn't find MI in its own basic block?");
197 Offset += TII->GetInstSizeInBytes(*I);
197 Offset += TII->getInstSizeInBytes(*I);
198198 }
199199 return Offset;
200200 }
419419 MachineBasicBlock *NewBB = splitBlockBeforeInstr(MI);
420420 // No need for the branch to the next block. We're adding an unconditional
421421 // branch to the destination.
422 int delta = TII->GetInstSizeInBytes(MBB->back());
422 int delta = TII->getInstSizeInBytes(MBB->back());
423423 BlockInfo[MBB->getNumber()].Size -= delta;
424424 MBB->back().eraseFromParent();
425425 // BlockInfo[SplitBB].Offset is wrong temporarily, fixed below
445445 if (MI->getOpcode() == AArch64::Bcc)
446446 invertBccCondition(MIB);
447447 MIB.addMBB(NextBB);
448 BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
448 BlockInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
449449 BuildMI(MBB, DebugLoc(), TII->get(AArch64::B)).addMBB(DestBB);
450 BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
450 BlockInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
451451
452452 // Remove the old conditional branch. It may or may not still be in MBB.
453 BlockInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI);
453 BlockInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
454454 MI->eraseFromParent();
455455
456456 // Finally, keep the block offsets up to date.
3737
3838 /// GetInstSize - Return the number of bytes of code the specified
3939 /// instruction may be. This returns the maximum number of bytes.
40 unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
40 unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
4141 const MachineBasicBlock &MBB = *MI.getParent();
4242 const MachineFunction *MF = MBB.getParent();
4343 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
5757 return 0;
5858 }
5959
60 llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");
60 llvm_unreachable("getInstSizeInBytes()- Unable to determin insn size");
6161 }
6262
6363 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
3838 /// always be able to get register info as well (through this method).
3939 const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
4040
41 unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
41 unsigned getInstSizeInBytes(const MachineInstr &MI) const;
4242
4343 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
4444
609609
610610 /// GetInstSize - Return the size of the specified MachineInstr.
611611 ///
612 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
612 unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
613613 const MachineBasicBlock &MBB = *MI.getParent();
614614 const MachineFunction *MF = MBB.getParent();
615615 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
668668 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
669669 while (++I != E && I->isInsideBundle()) {
670670 assert(!I->isBundle() && "No nested bundle!");
671 Size += GetInstSizeInBytes(*I);
671 Size += getInstSizeInBytes(*I);
672672 }
673673 return Size;
674674 }
153153
154154 /// GetInstSize - Returns the size of the specified MachineInstr.
155155 ///
156 virtual unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
156 virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const;
157157
158158 unsigned isLoadFromStackSlot(const MachineInstr &MI,
159159 int &FrameIndex) const override;
4141 BBI.PostAlign = 0;
4242
4343 for (MachineInstr &I : *MBB) {
44 BBI.Size += TII->GetInstSizeInBytes(I);
45 // For inline asm, GetInstSizeInBytes returns a conservative estimate.
44 BBI.Size += TII->getInstSizeInBytes(I);
45 // For inline asm, getInstSizeInBytes returns a conservative estimate.
4646 // The actual size may be smaller, but still a multiple of the instr size.
4747 if (I.isInlineAsm())
4848 BBI.Unalign = isThumb ? 1 : 2;
822822 // Sum instructions before MI in MBB.
823823 for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
824824 assert(I != MBB->end() && "Didn't find MI in its own basic block?");
825 Offset += TII->GetInstSizeInBytes(*I);
825 Offset += TII->getInstSizeInBytes(*I);
826826 }
827827 return Offset;
828828 }
13301330 // iterates at least once.
13311331 BaseInsertOffset =
13321332 std::max(UserBBI.postOffset() - UPad - 8,
1333 UserOffset + TII->GetInstSizeInBytes(*UserMI) + 1);
1333 UserOffset + TII->getInstSizeInBytes(*UserMI) + 1);
13341334 DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
13351335 }
13361336 unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad +
13401340 unsigned CPUIndex = CPUserIndex+1;
13411341 unsigned NumCPUsers = CPUsers.size();
13421342 MachineInstr *LastIT = nullptr;
1343 for (unsigned Offset = UserOffset + TII->GetInstSizeInBytes(*UserMI);
1343 for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI);
13441344 Offset < BaseInsertOffset;
1345 Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) {
1345 Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) {
13461346 assert(MI != UserMBB->end() && "Fell off end of block");
13471347 if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == &*MI) {
13481348 CPUser &U = CPUsers[CPUIndex];
16431643 splitBlockBeforeInstr(MI);
16441644 // No need for the branch to the next block. We're adding an unconditional
16451645 // branch to the destination.
1646 int delta = TII->GetInstSizeInBytes(MBB->back());
1646 int delta = TII->getInstSizeInBytes(MBB->back());
16471647 BBInfo[MBB->getNumber()].Size -= delta;
16481648 MBB->back().eraseFromParent();
16491649 // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
16591659 BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
16601660 .addMBB(NextBB).addImm(CC).addReg(CCReg);
16611661 Br.MI = &MBB->back();
1662 BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
1662 BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
16631663 if (isThumb)
16641664 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)
16651665 .addImm(ARMCC::AL).addReg(0);
16661666 else
16671667 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1668 BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
1668 BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
16691669 unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
16701670 ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
16711671
16721672 // Remove the old conditional branch. It may or may not still be in MBB.
1673 BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI);
1673 BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
16741674 MI->eraseFromParent();
16751675 adjustBBOffsetsAfter(MBB);
16761676 return true;
20832083 }
20842084 }
20852085
2086 unsigned NewSize = TII->GetInstSizeInBytes(*NewJTMI);
2087 unsigned OrigSize = TII->GetInstSizeInBytes(*MI);
2086 unsigned NewSize = TII->getInstSizeInBytes(*NewJTMI);
2087 unsigned OrigSize = TII->getInstSizeInBytes(*MI);
20882088 MI->eraseFromParent();
20892089
20902090 int Delta = OrigSize - NewSize + DeadSize;
13581358 unsigned FnSize = 0;
13591359 for (auto &MBB : MF) {
13601360 for (auto &MI : MBB)
1361 FnSize += TII.GetInstSizeInBytes(MI);
1361 FnSize += TII.getInstSizeInBytes(MI);
13621362 }
13631363 return FnSize;
13641364 }
237237 //===---------------------------------------------------------------------===//
238238
239239 Rather than having tBR_JTr print a ".align 2" and constant island pass pad it,
240 add a target specific ALIGN instruction instead. That way, GetInstSizeInBytes
240 add a target specific ALIGN instruction instead. That way, getInstSizeInBytes
241241 won't have to over-estimate. It can also be used for loop alignment pass.
242242
243243 //===---------------------------------------------------------------------===//
438438 return false;
439439 }
440440
441 unsigned AVRInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
441 unsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
442442 unsigned Opcode = MI->getOpcode();
443443
444444 switch (Opcode) {
6969 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
7070 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
7171 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
72 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
72 unsigned getInstSizeInBytes(const MachineInstr *MI) const;
7373
7474 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
7575 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
6969 for (MachineBasicBlock &MBB : Fn) {
7070 unsigned BlockSize = 0;
7171 for (MachineInstr &MI : MBB)
72 BlockSize += TII->GetInstSizeInBytes(MI);
72 BlockSize += TII->getInstSizeInBytes(MI);
7373
7474 BlockSizes[MBB.getNumber()] = BlockSize;
7575 FuncSize += BlockSize;
106106 I != E; ++I) {
107107 if ((I->getOpcode() != MSP430::JCC || I->getOperand(0).isImm()) &&
108108 I->getOpcode() != MSP430::JMP) {
109 MBBStartOffset += TII->GetInstSizeInBytes(*I);
109 MBBStartOffset += TII->getInstSizeInBytes(*I);
110110 continue;
111111 }
112112
292292 /// GetInstSize - Return the number of bytes of code the specified
293293 /// instruction may be. This returns the maximum number of bytes.
294294 ///
295 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
295 unsigned MSP430InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
296296 const MCInstrDesc &Desc = MI.getDesc();
297297
298298 switch (Desc.TSFlags & MSP430II::SizeMask) {
6767 const TargetRegisterClass *RC,
6868 const TargetRegisterInfo *TRI) const override;
6969
70 unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
70 unsigned getInstSizeInBytes(const MachineInstr &MI) const;
7171
7272 // Branch folding goodness
7373 bool
800800 BBI.Size = 0;
801801
802802 for (const MachineInstr &MI : *MBB)
803 BBI.Size += TII->GetInstSizeInBytes(MI);
803 BBI.Size += TII->getInstSizeInBytes(MI);
804804 }
805805
806806 /// getOffsetOf - Return the current offset of the specified machine instruction
817817 // Sum instructions before MI in MBB.
818818 for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
819819 assert(I != MBB->end() && "Didn't find MI in its own basic block?");
820 Offset += TII->GetInstSizeInBytes(*I);
820 Offset += TII->getInstSizeInBytes(*I);
821821 }
822822 return Offset;
823823 }
12961296 unsigned CPUIndex = CPUserIndex+1;
12971297 unsigned NumCPUsers = CPUsers.size();
12981298 //MachineInstr *LastIT = 0;
1299 for (unsigned Offset = UserOffset + TII->GetInstSizeInBytes(*UserMI);
1299 for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI);
13001300 Offset < BaseInsertOffset;
1301 Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) {
1301 Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) {
13021302 assert(MI != UserMBB->end() && "Fell off end of block");
13031303 if (CPUIndex < NumCPUsers &&
13041304 CPUsers[CPUIndex].MI == static_cast(MI)) {
16211621 splitBlockBeforeInstr(*MI);
16221622 // No need for the branch to the next block. We're adding an unconditional
16231623 // branch to the destination.
1624 int delta = TII->GetInstSizeInBytes(MBB->back());
1624 int delta = TII->getInstSizeInBytes(MBB->back());
16251625 BBInfo[MBB->getNumber()].Size -= delta;
16261626 MBB->back().eraseFromParent();
16271627 // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
16431643 .addMBB(NextBB);
16441644 }
16451645 Br.MI = &MBB->back();
1646 BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
1646 BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
16471647 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1648 BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back());
1648 BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
16491649 unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
16501650 ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
16511651
16521652 // Remove the old conditional branch. It may or may not still be in MBB.
1653 BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI);
1653 BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
16541654 MI->eraseFromParent();
16551655 adjustBBOffsetsAfter(MBB);
16561656 return true;
601601 // Get instruction with delay slot.
602602 MachineBasicBlock::instr_iterator DSI = I.getInstrIterator();
603603
604 if (InMicroMipsMode && TII->GetInstSizeInBytes(*std::next(DSI)) == 2 &&
604 if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 &&
605605 DSI->isCall()) {
606606 // If instruction in delay slot is 16b change opcode to
607607 // corresponding instruction with short delay slot.
691691 bool InMicroMipsMode = STI.inMicroMipsMode();
692692 const MipsInstrInfo *TII = STI.getInstrInfo();
693693 unsigned Opcode = (*Slot).getOpcode();
694 if (InMicroMipsMode && TII->GetInstSizeInBytes(*CurrI) == 2 &&
694 if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 &&
695695 (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
696696 Opcode == Mips::PseudoReturn))
697697 continue;
397397 }
398398
399399 /// Return the number of bytes of code the specified instruction may be.
400 unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
400 unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
401401 switch (MI.getOpcode()) {
402402 default:
403403 return MI.getDesc().getSize();
9191 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
9292
9393 /// Return the number of bytes of code the specified instruction may be.
94 unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
94 unsigned getInstSizeInBytes(const MachineInstr &MI) const;
9595
9696 void storeRegToStackSlot(MachineBasicBlock &MBB,
9797 MachineBasicBlock::iterator MBBI,
178178 // Compute size of MBB.
179179 for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin();
180180 MI != MBB->instr_end(); ++MI)
181 MBBInfos[I].Size += TII->GetInstSizeInBytes(*MI);
181 MBBInfos[I].Size += TII->getInstSizeInBytes(*MI);
182182
183183 // Search for MBB's branch instruction.
184184 ReverseIter End = MBB->rend();
107107
108108 unsigned BlockSize = 0;
109109 for (MachineInstr &MI : *MBB)
110 BlockSize += TII->GetInstSizeInBytes(MI);
110 BlockSize += TII->getInstSizeInBytes(MI);
111111
112112 BlockSizes[MBB->getNumber()] = BlockSize;
113113 FuncSize += BlockSize;
154154 Dest = I->getOperand(0).getMBB();
155155
156156 if (!Dest) {
157 MBBStartOffset += TII->GetInstSizeInBytes(*I);
157 MBBStartOffset += TII->getInstSizeInBytes(*I);
158158 continue;
159159 }
160160
1124211242 uint64_t LoopSize = 0;
1124311243 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
1124411244 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J) {
11245 LoopSize += TII->GetInstSizeInBytes(*J);
11245 LoopSize += TII->getInstSizeInBytes(*J);
1124611246 if (LoopSize > 32)
1124711247 break;
1124811248 }
18071807 /// GetInstSize - Return the number of bytes of code the specified
18081808 /// instruction may be. This returns the maximum number of bytes.
18091809 ///
1810 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
1810 unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
18111811 unsigned Opcode = MI.getOpcode();
18121812
18131813 if (Opcode == PPC::INLINEASM) {
255255 /// GetInstSize - Return the number of bytes of code the specified
256256 /// instruction may be. This returns the maximum number of bytes.
257257 ///
258 unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
258 unsigned getInstSizeInBytes(const MachineInstr &MI) const;
259259
260260 void getNoopForMachoTarget(MCInst &NopInst) const override;
261261