llvm.org GIT mirror llvm / 7ad3e06
Switch over to TableGen generated register file description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7511 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 17 years ago
4 changed file(s) with 30 addition(s) and 276 deletion(s). Raw diff Collapse all Expand all
11 LIBRARYNAME = x86
22 include $(LEVEL)/Makefile.common
33
4
5
6 # Make sure that tblgen is run, first thing.
7 $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc X86GenRegisterInfo.inc
8
9 X86GenRegisterNames.inc: $(wildcard *.td) $(TBLGEN)
10 $(TBLGEN) X86.td -gen-register-enums -o $@
11
12 X86GenRegisterInfo.h.inc: $(wildcard *.td) $(TBLGEN)
13 $(TBLGEN) X86.td -gen-register-desc-header -o $@
14
15 X86GenRegisterInfo.inc: $(wildcard *.td) $(TBLGEN)
16 $(TBLGEN) X86.td -gen-register-desc -o $@
17
18 clean::
19 $(VERB) rm -f *.inc
20
2323 cl::desc("Disable frame pointer elimination optimization"));
2424 }
2525
26 X86RegisterInfo::X86RegisterInfo()
27 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
28
2629 static unsigned getIdx(const TargetRegisterClass *RC) {
2730 switch (RC->getSize()) {
2831 default: assert(0 && "Invalid data size!");
6467 MachineInstr *MI = BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg);
6568 MBBI = MBB.insert(MBBI, MI)+1;
6669 }
67
68 const unsigned* X86RegisterInfo::getCalleeSaveRegs() const {
69 static const unsigned CalleeSaveRegs[] = {
70 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
71 };
72 return CalleeSaveRegs;
73 }
74
7570
7671 //===----------------------------------------------------------------------===//
7772 // Stack Frame Processing methods
248243 }
249244 }
250245
251
252 //===----------------------------------------------------------------------===//
253 // Register Class Implementation Code
254 //===----------------------------------------------------------------------===//
255
256 //===----------------------------------------------------------------------===//
257 // 8 Bit Integer Registers
258 //
259 namespace {
260 const unsigned ByteRegClassRegs[] = {
261 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, X86::DH, X86::BH,
262 };
263
264 TargetRegisterClass X86ByteRegisterClassInstance(1, 1, ByteRegClassRegs,
265 ByteRegClassRegs+sizeof(ByteRegClassRegs)/sizeof(ByteRegClassRegs[0]));
266
267 //===----------------------------------------------------------------------===//
268 // 16 Bit Integer Registers
269 //
270 const unsigned ShortRegClassRegs[] = {
271 X86::AX, X86::CX, X86::DX, X86::BX, X86::SI, X86::DI, X86::BP, X86::SP
272 };
273
274 struct R16CL : public TargetRegisterClass {
275 R16CL():TargetRegisterClass(2, 2, ShortRegClassRegs, ShortRegClassRegs+8) {}
276 iterator allocation_order_end(MachineFunction &MF) const {
277 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
278 return end()-2; // Don't allocate SP or BP
279 else
280 return end()-1; // Don't allocate SP
281 }
282 } X86ShortRegisterClassInstance;
283
284 //===----------------------------------------------------------------------===//
285 // 32 Bit Integer Registers
286 //
287 const unsigned IntRegClassRegs[] = {
288 X86::EAX, X86::ECX, X86::EDX, X86::EBX,
289 X86::ESI, X86::EDI, X86::EBP, X86::ESP
290 };
291
292 struct R32CL : public TargetRegisterClass {
293 R32CL() : TargetRegisterClass(4, 4, IntRegClassRegs, IntRegClassRegs+8) {}
294 iterator allocation_order_end(MachineFunction &MF) const {
295 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
296 return end()-2; // Don't allocate ESP or EBP
297 else
298 return end()-1; // Don't allocate ESP
299 }
300 } X86IntRegisterClassInstance;
301
302 //===----------------------------------------------------------------------===//
303 // Pseudo Floating Point Registers
304 //
305 const unsigned PFPRegClassRegs[] = {
306 #define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
307 #include "X86RegisterInfo.def"
308 };
309
310 TargetRegisterClass X86FPRegisterClassInstance(10, 4, PFPRegClassRegs,
311 PFPRegClassRegs+sizeof(PFPRegClassRegs)/sizeof(PFPRegClassRegs[0]));
312
313 //===----------------------------------------------------------------------===//
314 // Register class array...
315 //
316 const TargetRegisterClass * const X86RegClasses[] = {
317 &X86ByteRegisterClassInstance,
318 &X86ShortRegisterClassInstance,
319 &X86IntRegisterClassInstance,
320 &X86FPRegisterClassInstance,
321 };
322 }
323
324
325 // Create static lists to contain register alias sets...
326 #define ALIASLIST(NAME, ...) \
327 static const unsigned NAME[] = { __VA_ARGS__ };
328 #include "X86RegisterInfo.def"
329
330
331 // X86Regs - Turn the X86RegisterInfo.def file into a bunch of register
332 // descriptors
333 //
334 static const MRegisterDesc X86Regs[] = {
335 #define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
336 { NAME, ALIAS_SET, FLAGS, TSFLAGS },
337 #include "X86RegisterInfo.def"
338 };
339
340 X86RegisterInfo::X86RegisterInfo()
341 : MRegisterInfo(X86Regs, sizeof(X86Regs)/sizeof(X86Regs[0]),
342 X86RegClasses,
343 X86RegClasses+sizeof(X86RegClasses)/sizeof(X86RegClasses[0]),
344 X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {
345 }
346
347
246 #include "X86GenRegisterInfo.inc"
348247
349248 const TargetRegisterClass*
350249 X86RegisterInfo::getRegClassForType(const Type* Ty) const {
354253 default: assert(0 && "Invalid type to getClass!");
355254 case Type::BoolTyID:
356255 case Type::SByteTyID:
357 case Type::UByteTyID: return &X86ByteRegisterClassInstance;
256 case Type::UByteTyID: return &r8Instance;
358257 case Type::ShortTyID:
359 case Type::UShortTyID: return &X86ShortRegisterClassInstance;
258 case Type::UShortTyID: return &r16Instance;
360259 case Type::IntTyID:
361260 case Type::UIntTyID:
362 case Type::PointerTyID: return &X86IntRegisterClassInstance;
261 case Type::PointerTyID: return &r32Instance;
363262
364263 case Type::FloatTyID:
365 case Type::DoubleTyID: return &X86FPRegisterClassInstance;
366 }
367 }
264 case Type::DoubleTyID: return &rFPInstance;
265 }
266 }
+0
-161
lib/Target/X86/X86RegisterInfo.def less more
None //===-- X86RegisterInfo.def - X86 Register Information ----------*- C++ -*-===//
1 //
2 // This file describes all of the registers that the X86 backend uses. It relies
3 // on an external 'R' macro being defined that takes the arguments specified
4 // below, and is used to make all of the information relevant to registers be in
5 // one place.
6 //
7 //===----------------------------------------------------------------------===//
8
9 // NOTE: No include guards desired
10 #ifndef R
11 #define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
12 #endif
13
14 #ifndef R8
15 #define R8(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
16 R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
17 #endif
18
19 #ifndef R16
20 #define R16(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
21 R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
22 #endif
23
24 #ifndef R32
25 #define R32(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
26 R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
27 #endif
28
29 // Pseudo Floating Point registers
30 #ifndef PFP
31 #define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
32 R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
33 #endif
34
35 // Floating Point Stack registers
36 #ifndef FPS
37 #define FPS(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
38 R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
39 #endif
40
41 // Arguments passed into the R macros
42 // #1: Enum Name - This ends up being a symbol in the X86 namespace
43 // #2: Register name - The name of the register as used by the gnu assembler
44 // #3: Register Flags - A bitfield of flags or'd together from the
45 // MRegisterInfo.h file.
46 // #4: Target Specific Flags - Another bitfield containing X86 specific flags
47 // as necessary.
48 // #5: Alias set for registers aliased to this register (sets defined below).
49
50
51 // The first register must always be a 'noop' register for all backends. This
52 // is used as the destination register for instructions that do not produce a
53 // value. Some frontends may use this as an operand register to mean special
54 // things, for example, the Sparc backend uses R#0 to mean %g0 which always
55 // PRODUCES the value 0.
56 //
57 // The X86 backend uses this value as an operand register only in memory
58 // references where it means that there is no base or index register.
59 //
60 R(NoReg,"none", 0, 0, 0/*noalias*/)
61
62 // 32 bit registers, ordered as the processor does...
63 R32(EAX, "EAX", MVT::i32, 0, A_EAX)
64 R32(ECX, "ECX", MVT::i32, 0, A_ECX)
65 R32(EDX, "EDX", MVT::i32, 0, A_EDX)
66 R32(EBX, "EBX", MVT::i32, 0, A_EBX)
67 R32(ESP, "ESP", MVT::i32, 0, A_ESP)
68 R32(EBP, "EBP", MVT::i32, 0, A_EBP)
69 R32(ESI, "ESI", MVT::i32, 0, A_ESI)
70 R32(EDI, "EDI", MVT::i32, 0, A_EDI)
71
72 // 16 bit registers, aliased with the corresponding 32 bit registers above
73 R16( AX, "AX" , MVT::i16, 0, A_AX)
74 R16( CX, "CX" , MVT::i16, 0, A_CX)
75 R16( DX, "DX" , MVT::i16, 0, A_DX)
76 R16( BX, "BX" , MVT::i16, 0, A_BX)
77 R16( SP, "SP" , MVT::i16, 0, A_SP)
78 R16( BP, "BP" , MVT::i16, 0, A_BP)
79 R16( SI, "SI" , MVT::i16, 0, A_SI)
80 R16( DI, "DI" , MVT::i16, 0, A_DI)
81
82 // 8 bit registers aliased with registers above as well
83 R8 ( AL, "AL" , MVT::i8 , 0, A_AL)
84 R8 ( CL, "CL" , MVT::i8 , 0, A_CL)
85 R8 ( DL, "DL" , MVT::i8 , 0, A_DL)
86 R8 ( BL, "BL" , MVT::i8 , 0, A_BL)
87 R8 ( AH, "AH" , MVT::i8 , 0, A_AH)
88 R8 ( CH, "CH" , MVT::i8 , 0, A_CH)
89 R8 ( DH, "DH" , MVT::i8 , 0, A_DH)
90 R8 ( BH, "BH" , MVT::i8 , 0, A_BH)
91
92 // Pseudo Floating Point Registers
93 PFP(FP0, "FP0", MVT::f80 , 0, 0 /*noalias*/)
94 PFP(FP1, "FP1", MVT::f80 , 0, 0 /*noalias*/)
95 PFP(FP2, "FP2", MVT::f80 , 0, 0 /*noalias*/)
96 PFP(FP3, "FP3", MVT::f80 , 0, 0 /*noalias*/)
97 PFP(FP4, "FP4", MVT::f80 , 0, 0 /*noalias*/)
98 PFP(FP5, "FP5", MVT::f80 , 0, 0 /*noalias*/)
99 PFP(FP6, "FP6", MVT::f80 , 0, 0 /*noalias*/)
100
101 // Floating point stack registers
102 FPS(ST0, "ST(0)", MVT::f80, 0, 0)
103 FPS(ST1, "ST(1)", MVT::f80, 0, 0)
104 FPS(ST2, "ST(2)", MVT::f80, 0, 0)
105 FPS(ST3, "ST(3)", MVT::f80, 0, 0)
106 FPS(ST4, "ST(4)", MVT::f80, 0, 0)
107 FPS(ST5, "ST(5)", MVT::f80, 0, 0)
108 FPS(ST6, "ST(6)", MVT::f80, 0, 0)
109 FPS(ST7, "ST(7)", MVT::f80, 0, 0)
110
111 // Flags, Segment registers, etc...
112
113 // This is a slimy hack to make it possible to say that flags are clobbered...
114 // Ideally we'd model instructions based on which particular flag(s) they
115 // could clobber.
116 R(EFLAGS, "EFLAGS", MVT::i16, 0, 0 /*noalias*/)
117
118
119 //===----------------------------------------------------------------------===//
120 // Register alias set handling...
121 //
122
123 // Macro to handle definitions of alias sets that registers use...
124 #ifndef ALIASLIST
125 #define ALIASLIST(NAME, ...)
126 #endif
127
128 ALIASLIST(A_EAX , X86::AX, X86::AH, X86::AL, 0)
129 ALIASLIST(A_ECX , X86::CX, X86::CH, X86::CL, 0)
130 ALIASLIST(A_EDX , X86::DX, X86::DH, X86::DL, 0)
131 ALIASLIST(A_EBX , X86::BX, X86::BH, X86::BL, 0)
132 ALIASLIST(A_ESP , X86::SP, 0)
133 ALIASLIST(A_EBP , X86::BP, 0)
134 ALIASLIST(A_ESI , X86::SI, 0)
135 ALIASLIST(A_EDI , X86::DI, 0)
136 ALIASLIST(A_AX , X86::EAX, X86::AH, X86::AL, 0)
137 ALIASLIST(A_CX , X86::ECX, X86::CH, X86::CL, 0)
138 ALIASLIST(A_DX , X86::EDX, X86::DH, X86::DL, 0)
139 ALIASLIST(A_BX , X86::EBX, X86::BH, X86::BL, 0)
140 ALIASLIST(A_SP , X86::ESP, 0)
141 ALIASLIST(A_BP , X86::EBP, 0)
142 ALIASLIST(A_SI , X86::ESI, 0)
143 ALIASLIST(A_DI , X86::EDI, 0)
144 ALIASLIST(A_AL , X86::EAX, X86::AX, 0)
145 ALIASLIST(A_CL , X86::ECX, X86::CX, 0)
146 ALIASLIST(A_DL , X86::EDX, X86::DX, 0)
147 ALIASLIST(A_BL , X86::EBX, X86::BX, 0)
148 ALIASLIST(A_AH , X86::EAX, X86::AX, 0)
149 ALIASLIST(A_CH , X86::ECX, X86::CX, 0)
150 ALIASLIST(A_DH , X86::EDX, X86::DX, 0)
151 ALIASLIST(A_BH , X86::EBX, X86::BX, 0)
152 #undef ALIASLIST
153
154 // We are now done with the R* macros
155 #undef R
156 #undef R8
157 #undef R16
158 #undef R32
159 #undef PFP
160 #undef FPS
1010
1111 class Type;
1212
13 struct X86RegisterInfo : public MRegisterInfo {
13 #include "X86GenRegisterInfo.h.inc"
14
15 struct X86RegisterInfo : public X86GenRegisterInfo {
1416 X86RegisterInfo();
15
16 const unsigned* getCalleeSaveRegs() const;
17
1817 const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
1918
2019 /// Code Generation virtual methods...