llvm.org GIT mirror llvm / 7ac9cdf
Simplify extract element of a scalar to vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62383 91177308-0d34-0410-b5e6-96231b3b80d8 Mon P Wang 11 years ago
2 changed file(s) with 28 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
48774877 }
48784878
48794879 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
4880 // (vextract (scalar_to_vector val, 0) -> val
4881 SDValue InVec = N->getOperand(0);
4882 SDValue EltNo = N->getOperand(1);
4883
4884 if (isa(EltNo)) {
4885 unsigned Elt = cast(EltNo)->getZExtValue();
4886 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && Elt == 0) {
4887 return InVec.getOperand(0);
4888 }
4889 }
4890
4891 // Perform only after legalization to ensure build_vector / vector_shuffle
4892 // optimizations have already been done.
4893 if (!LegalOperations) return SDValue();
4894
48804895 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
48814896 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
48824897 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
4883
4884 // Perform only after legalization to ensure build_vector / vector_shuffle
4885 // optimizations have already been done.
4886 if (!LegalOperations) return SDValue();
4887
4888 SDValue InVec = N->getOperand(0);
4889 SDValue EltNo = N->getOperand(1);
48904898
48914899 if (isa(EltNo)) {
48924900 unsigned Elt = cast(EltNo)->getZExtValue();
0 ; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx -o %t -f
1 ; RUN: not grep movq %t
2
3 ; Check that widening doesn't introduce a mmx register in this case when
4 ; a simple load/store would suffice.
5
6 define void @foo(<2 x i16>* %A, <2 x i16>* %B) {
7 entry:
8 %tmp1 = load <2 x i16>* %A ; <<2 x i16>> [#uses=1]
9 store <2 x i16> %tmp1, <2 x i16>* %B
10 ret void
11 }
12