llvm.org GIT mirror llvm / 7abf67a
Add register encoding support in X86 backend - Add 'HwEncoding' for X86 registers and call getEncodingValue() to retrieve their encoding values. - This's the first step to adopt new scheme. Furthur revising is onging. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165241 91177308-0d34-0410-b5e6-96231b3b80d8 Michael Liao 8 years ago
8 changed file(s) with 288 addition(s) and 404 deletion(s). Raw diff Collapse all Expand all
1515 #include "MCTargetDesc/X86BaseInfo.h"
1616 #include "MCTargetDesc/X86FixupKinds.h"
1717 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
1819 #include "llvm/MC/MCExpr.h"
1920 #include "llvm/MC/MCInst.h"
2021 #include "llvm/MC/MCInstrInfo.h"
5051 return (STI.getFeatureBits() & X86::Mode64Bit) == 0;
5152 }
5253
53 static unsigned GetX86RegNum(const MCOperand &MO) {
54 return X86_MC::getX86RegNum(MO.getReg());
54 unsigned GetX86RegNum(const MCOperand &MO) const {
55 return Ctx.getRegisterInfo().getEncodingValue(MO.getReg()) & 0x7;
5556 }
5657
5758 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
6364 // VEX.VVVV => XMM9 => ~9
6465 //
6566 // See table 4-35 of Intel AVX Programming Reference for details.
66 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
67 unsigned OpNum) {
67 unsigned char getVEXRegisterEncoding(const MCInst &MI,
68 unsigned OpNum) const {
6869 unsigned SrcReg = MI.getOperand(OpNum).getReg();
6970 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
7071 if (X86II::isX86_64ExtendedReg(SrcReg))
208208 return DWARFFlavour::X86_32_Generic;
209209 }
210210
211 /// getX86RegNum - This function maps LLVM register identifiers to their X86
212 /// specific numbering, which is used in various places encoding instructions.
213 unsigned X86_MC::getX86RegNum(unsigned RegNo) {
214 switch(RegNo) {
215 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
216 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
217 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
218 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
219 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
220 return N86::ESP;
221 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
222 return N86::EBP;
223 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
224 return N86::ESI;
225 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
226 return N86::EDI;
227
228 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
229 return N86::EAX;
230 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
231 return N86::ECX;
232 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
233 return N86::EDX;
234 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
235 return N86::EBX;
236 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
237 return N86::ESP;
238 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
239 return N86::EBP;
240 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
241 return N86::ESI;
242 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
243 return N86::EDI;
244
245 case X86::ST0: return 0;
246 case X86::ST1: return 1;
247 case X86::ST2: return 2;
248 case X86::ST3: return 3;
249 case X86::ST4: return 4;
250 case X86::ST5: return 5;
251 case X86::ST6: return 6;
252 case X86::ST7: return 7;
253
254 case X86::XMM0: case X86::XMM8:
255 case X86::YMM0: case X86::YMM8: case X86::MM0:
256 return 0;
257 case X86::XMM1: case X86::XMM9:
258 case X86::YMM1: case X86::YMM9: case X86::MM1:
259 return 1;
260 case X86::XMM2: case X86::XMM10:
261 case X86::YMM2: case X86::YMM10: case X86::MM2:
262 return 2;
263 case X86::XMM3: case X86::XMM11:
264 case X86::YMM3: case X86::YMM11: case X86::MM3:
265 return 3;
266 case X86::XMM4: case X86::XMM12:
267 case X86::YMM4: case X86::YMM12: case X86::MM4:
268 return 4;
269 case X86::XMM5: case X86::XMM13:
270 case X86::YMM5: case X86::YMM13: case X86::MM5:
271 return 5;
272 case X86::XMM6: case X86::XMM14:
273 case X86::YMM6: case X86::YMM14: case X86::MM6:
274 return 6;
275 case X86::XMM7: case X86::XMM15:
276 case X86::YMM7: case X86::YMM15: case X86::MM7:
277 return 7;
278
279 case X86::ES: return 0;
280 case X86::CS: return 1;
281 case X86::SS: return 2;
282 case X86::DS: return 3;
283 case X86::FS: return 4;
284 case X86::GS: return 5;
285
286 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
287 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
288 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
289 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
290 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
291 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
292 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
293 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
294
295 // Pseudo index registers are equivalent to a "none"
296 // scaled index (See Intel Manual 2A, table 2-3)
297 case X86::EIZ:
298 case X86::RIZ:
299 return 4;
300
301 default:
302 assert((int(RegNo) > 0) && "Unknown physical register!");
303 return 0;
304 }
305 }
306
307211 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
308212 // FIXME: TableGen these.
309213 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
310 int SEH = X86_MC::getX86RegNum(Reg);
311 switch (Reg) {
312 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
313 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
314 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
315 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
316 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
317 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
318 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
319 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
320 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
321 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
322 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
323 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
324 SEH += 8;
325 break;
326 }
214 unsigned SEH = MRI->getEncodingValue(Reg);
327215 MRI->mapLLVMRegToSEHReg(Reg, SEH);
328216 }
329217 }
6363
6464 unsigned getDwarfRegFlavour(StringRef TT, bool isEH);
6565
66 unsigned getX86RegNum(unsigned RegNo);
67
6866 void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
6967
7068 /// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
108108 void emitMemModRMByte(const MachineInstr &MI,
109109 unsigned Op, unsigned RegOpcodeField,
110110 intptr_t PCAdj = 0);
111
112 unsigned getX86RegNum(unsigned RegNo) const {
113 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
114 return TRI->getEncodingValue(RegNo) & 0x7;
115 }
116
117 unsigned char getVEXRegisterEncoding(const MachineInstr &MI,
118 unsigned OpNum) const;
111119 };
112120
113121 template
362370 template
363371 void Emitter::emitRegModRMByte(unsigned ModRMReg,
364372 unsigned RegOpcodeFld){
365 MCE.emitByte(ModRMByte(3, RegOpcodeFld, X86_MC::getX86RegNum(ModRMReg)));
373 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
366374 }
367375
368376 template
500508 // 2-7) and absolute references.
501509 unsigned BaseRegNo = -1U;
502510 if (BaseReg != 0 && BaseReg != X86::RIP)
503 BaseRegNo = X86_MC::getX86RegNum(BaseReg);
511 BaseRegNo = getX86RegNum(BaseReg);
504512
505513 if (// The SIB byte must be used if there is an index register.
506514 IndexReg.getReg() == 0 &&
576584 // Manual 2A, table 2-7. The displacement has already been output.
577585 unsigned IndexRegNo;
578586 if (IndexReg.getReg())
579 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
587 IndexRegNo = getX86RegNum(IndexReg.getReg());
580588 else // Examples: [ESP+1*+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
581589 IndexRegNo = 4;
582590 emitSIBByte(SS, IndexRegNo, 5);
583591 } else {
584 unsigned BaseRegNo = X86_MC::getX86RegNum(BaseReg);
592 unsigned BaseRegNo = getX86RegNum(BaseReg);
585593 unsigned IndexRegNo;
586594 if (IndexReg.getReg())
587 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
595 IndexRegNo = getX86RegNum(IndexReg.getReg());
588596 else
589597 IndexRegNo = 4; // For example [ESP+1*+4]
590598 emitSIBByte(SS, IndexRegNo, BaseRegNo);
755763 // VEX.VVVV => XMM9 => ~9
756764 //
757765 // See table 4-35 of Intel AVX Programming Reference for details.
758 static unsigned char getVEXRegisterEncoding(const MachineInstr &MI,
759 unsigned OpNum) {
766 template
767 unsigned char
768 Emitter::getVEXRegisterEncoding(const MachineInstr &MI,
769 unsigned OpNum) const {
760770 unsigned SrcReg = MI.getOperand(OpNum).getReg();
761 unsigned SrcRegNum = X86_MC::getX86RegNum(MI.getOperand(OpNum).getReg());
771 unsigned SrcRegNum = getX86RegNum(MI.getOperand(OpNum).getReg());
762772 if (X86II::isX86_64ExtendedReg(SrcReg))
763773 SrcRegNum |= 8;
764774
12341244
12351245 case X86II::AddRegFrm: {
12361246 MCE.emitByte(BaseOpcode +
1237 X86_MC::getX86RegNum(MI.getOperand(CurOp++).getReg()));
1247 getX86RegNum(MI.getOperand(CurOp++).getReg()));
12381248
12391249 if (CurOp == NumOps)
12401250 break;
12691279 case X86II::MRMDestReg: {
12701280 MCE.emitByte(BaseOpcode);
12711281 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
1272 X86_MC::getX86RegNum(MI.getOperand(CurOp+1).getReg()));
1282 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
12731283 CurOp += 2;
12741284 break;
12751285 }
12801290 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
12811291 SrcRegNum++;
12821292 emitMemModRMByte(MI, CurOp,
1283 X86_MC::getX86RegNum(MI.getOperand(SrcRegNum).getReg()));
1293 getX86RegNum(MI.getOperand(SrcRegNum).getReg()));
12841294 CurOp = SrcRegNum + 1;
12851295 break;
12861296 }
12961306 ++SrcRegNum;
12971307
12981308 emitRegModRMByte(MI.getOperand(SrcRegNum).getReg(),
1299 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
1309 getX86RegNum(MI.getOperand(CurOp).getReg()));
13001310 // 2 operands skipped with HasMemOp4, compensate accordingly
13011311 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
13021312 if (HasVEX_4VOp3)
13181328 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
13191329 X86II::getSizeOfImm(Desc->TSFlags) : 0;
13201330 emitMemModRMByte(MI, FirstMemOp,
1321 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj);
1331 getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj);
13221332 CurOp += AddrOperands + 1;
13231333 if (HasVEX_4VOp3)
13241334 ++CurOp;
14081418 MCE.emitByte(BaseOpcode);
14091419 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
14101420 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
1411 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
1421 getX86RegNum(MI.getOperand(CurOp).getReg()));
14121422 ++CurOp;
14131423 break;
14141424
14411451 const MachineOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
14421452 : CurOp);
14431453 ++CurOp;
1444 unsigned RegNum = X86_MC::getX86RegNum(MO.getReg()) << 4;
1454 unsigned RegNum = getX86RegNum(MO.getReg()) << 4;
14451455 if (X86II::isX86_64ExtendedReg(MO.getReg()))
14461456 RegNum |= 1 << 7;
14471457 // If there is an additional 5th operand it must be an immediate, which
1041110411 DebugLoc dl = Op.getDebugLoc();
1041210412
1041310413 const Value *TrmpAddr = cast(Op.getOperand(4))->getValue();
10414 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
1041410415
1041510416 if (Subtarget->is64Bit()) {
1041610417 SDValue OutChains[6];
1041910420 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
1042010421 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
1042110422
10422 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
10423 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
10423 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
10424 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
1042410425
1042510426 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
1042610427
1052210523
1052310524 // This is storing the opcode for MOV32ri.
1052410525 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10525 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
10526 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
1052610527 OutChains[0] = DAG.getStore(Root, dl,
1052710528 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
1052810529 Trmp, MachinePointerInfo(TrmpAddr),
105105
106106 int
107107 X86RegisterInfo::getSEHRegNum(unsigned i) const {
108 int reg = X86_MC::getX86RegNum(i);
109 switch (i) {
110 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
112 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
113 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
114 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
115 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
116 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
117 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
118 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
119 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
120 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
121 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
122 reg += 8;
123 }
124 return reg;
108 return getEncodingValue(i);
125109 }
126110
127111 const TargetRegisterClass *
5656
5757 public:
5858 X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
59
60 /// getX86RegNum - Returns the native X86 register number for the given LLVM
61 /// register identifier.
62 static unsigned getX86RegNum(unsigned RegNo);
6359
6460 // FIXME: This should be tablegen'd like getDwarfRegNum is
6561 int getSEHRegNum(unsigned i) const;
1212 //
1313 //===----------------------------------------------------------------------===//
1414
15 //===----------------------------------------------------------------------===//
16 // Register definitions...
17 //
15 class X86Reg Enc, list subregs = []> : Register {
16 let Namespace = "X86";
17 let HWEncoding = Enc;
18 let SubRegs = subregs;
19 }
20
21 // Subregister indices.
1822 let Namespace = "X86" in {
19
20 // Subregister indices.
2123 def sub_8bit : SubRegIndex;
2224 def sub_8bit_hi : SubRegIndex;
2325 def sub_16bit : SubRegIndex;
2426 def sub_32bit : SubRegIndex;
25 def sub_xmm : SubRegIndex;
26
27
28 // In the register alias definitions below, we define which registers alias
29 // which others. We only specify which registers the small registers alias,
30 // because the register file generator is smart enough to figure out that
31 // AL aliases AX if we tell it that AX aliased AL (for example).
32
33 // Dwarf numbering is different for 32-bit and 64-bit, and there are
34 // variations by target as well. Currently the first entry is for X86-64,
35 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
36 // and debug information on X86-32/Darwin)
37
38 // 8-bit registers
39 // Low registers
40 def AL : Register<"al">;
41 def DL : Register<"dl">;
42 def CL : Register<"cl">;
43 def BL : Register<"bl">;
44
45 // X86-64 only, requires REX.
46 let CostPerUse = 1 in {
47 def SIL : Register<"sil">;
48 def DIL : Register<"dil">;
49 def BPL : Register<"bpl">;
50 def SPL : Register<"spl">;
51 def R8B : Register<"r8b">;
52 def R9B : Register<"r9b">;
53 def R10B : Register<"r10b">;
54 def R11B : Register<"r11b">;
55 def R12B : Register<"r12b">;
56 def R13B : Register<"r13b">;
57 def R14B : Register<"r14b">;
58 def R15B : Register<"r15b">;
59 }
60
61 // High registers. On x86-64, these cannot be used in any instruction
62 // with a REX prefix.
63 def AH : Register<"ah">;
64 def DH : Register<"dh">;
65 def CH : Register<"ch">;
66 def BH : Register<"bh">;
67
68 // 16-bit registers
69 let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
70 def AX : RegisterWithSubRegs<"ax", [AL,AH]>;
71 def DX : RegisterWithSubRegs<"dx", [DL,DH]>;
72 def CX : RegisterWithSubRegs<"cx", [CL,CH]>;
73 def BX : RegisterWithSubRegs<"bx", [BL,BH]>;
74 }
75 let SubRegIndices = [sub_8bit] in {
76 def SI : RegisterWithSubRegs<"si", [SIL]>;
77 def DI : RegisterWithSubRegs<"di", [DIL]>;
78 def BP : RegisterWithSubRegs<"bp", [BPL]>;
79 def SP : RegisterWithSubRegs<"sp", [SPL]>;
80 }
81 def IP : Register<"ip">;
82
83 // X86-64 only, requires REX.
84 let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
85 def R8W : RegisterWithSubRegs<"r8w", [R8B]>;
86 def R9W : RegisterWithSubRegs<"r9w", [R9B]>;
87 def R10W : RegisterWithSubRegs<"r10w", [R10B]>;
88 def R11W : RegisterWithSubRegs<"r11w", [R11B]>;
89 def R12W : RegisterWithSubRegs<"r12w", [R12B]>;
90 def R13W : RegisterWithSubRegs<"r13w", [R13B]>;
91 def R14W : RegisterWithSubRegs<"r14w", [R14B]>;
92 def R15W : RegisterWithSubRegs<"r15w", [R15B]>;
93 }
94 // 32-bit registers
95 let SubRegIndices = [sub_16bit] in {
96 def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[-2, 0, 0]>;
97 def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[-2, 2, 2]>;
98 def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[-2, 1, 1]>;
99 def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[-2, 3, 3]>;
100 def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[-2, 6, 6]>;
101 def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[-2, 7, 7]>;
102 def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[-2, 4, 5]>;
103 def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[-2, 5, 4]>;
104 def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[-2, 8, 8]>;
105
106 // X86-64 only, requires REX
107 let CostPerUse = 1 in {
108 def R8D : RegisterWithSubRegs<"r8d", [R8W]>;
109 def R9D : RegisterWithSubRegs<"r9d", [R9W]>;
110 def R10D : RegisterWithSubRegs<"r10d", [R10W]>;
111 def R11D : RegisterWithSubRegs<"r11d", [R11W]>;
112 def R12D : RegisterWithSubRegs<"r12d", [R12W]>;
113 def R13D : RegisterWithSubRegs<"r13d", [R13W]>;
114 def R14D : RegisterWithSubRegs<"r14d", [R14W]>;
115 def R15D : RegisterWithSubRegs<"r15d", [R15W]>;
116 }}
117
118 // 64-bit registers, X86-64 only
119 let SubRegIndices = [sub_32bit] in {
120 def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
121 def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
122 def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
123 def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
124 def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
125 def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
126 def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
127 def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
128
129 // These also require REX.
130 let CostPerUse = 1 in {
131 def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
132 def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
133 def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
134 def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
135 def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
136 def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
137 def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
138 def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
139 def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
140 }}
141
142 // MMX Registers. These are actually aliased to ST0 .. ST7
143 def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
144 def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
145 def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
146 def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
147 def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
148 def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
149 def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
150 def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
151
152 // Pseudo Floating Point registers
153 def FP0 : Register<"fp0">;
154 def FP1 : Register<"fp1">;
155 def FP2 : Register<"fp2">;
156 def FP3 : Register<"fp3">;
157 def FP4 : Register<"fp4">;
158 def FP5 : Register<"fp5">;
159 def FP6 : Register<"fp6">;
160
161 // XMM Registers, used by the various SSE instruction set extensions.
162 def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
163 def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
164 def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
165 def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
166 def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
167 def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
168 def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
169 def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
170
171 // X86-64 only
172 let CostPerUse = 1 in {
173 def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
174 def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
175 def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
176 def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
177 def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
178 def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
179 def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
180 def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
181 } // CostPerUse
182
183 // YMM Registers, used by AVX instructions
184 let SubRegIndices = [sub_xmm] in {
185 def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegAlias;
186 def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegAlias;
187 def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegAlias;
188 def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegAlias;
189 def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegAlias;
190 def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegAlias;
191 def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegAlias;
192 def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegAlias;
193 def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegAlias;
194 def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegAlias;
195 def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegAlias;
196 def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegAlias;
197 def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegAlias;
198 def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegAlias;
199 def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegAlias;
200 def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegAlias;
201 }
202
203 class STRegister A> : Register {
204 let Aliases = A;
205 }
206
207 // Floating point stack registers. These don't map one-to-one to the FP
208 // pseudo registers, but we still mark them as aliasing FP registers. That
209 // way both kinds can be live without exceeding the stack depth. ST registers
210 // are only live around inline assembly.
211 def ST0 : STRegister<"st(0)", []>, DwarfRegNum<[33, 12, 11]>;
212 def ST1 : STRegister<"st(1)", [FP6]>, DwarfRegNum<[34, 13, 12]>;
213 def ST2 : STRegister<"st(2)", [FP5]>, DwarfRegNum<[35, 14, 13]>;
214 def ST3 : STRegister<"st(3)", [FP4]>, DwarfRegNum<[36, 15, 14]>;
215 def ST4 : STRegister<"st(4)", [FP3]>, DwarfRegNum<[37, 16, 15]>;
216 def ST5 : STRegister<"st(5)", [FP2]>, DwarfRegNum<[38, 17, 16]>;
217 def ST6 : STRegister<"st(6)", [FP1]>, DwarfRegNum<[39, 18, 17]>;
218 def ST7 : STRegister<"st(7)", [FP0]>, DwarfRegNum<[40, 19, 18]>;
219
220 // Floating-point status word
221 def FPSW : Register<"fpsw">;
222
223 // Status flags register
224 def EFLAGS : Register<"flags">;
225
226 // Segment registers
227 def CS : Register<"cs">;
228 def DS : Register<"ds">;
229 def SS : Register<"ss">;
230 def ES : Register<"es">;
231 def FS : Register<"fs">;
232 def GS : Register<"gs">;
233
234 // Debug registers
235 def DR0 : Register<"dr0">;
236 def DR1 : Register<"dr1">;
237 def DR2 : Register<"dr2">;
238 def DR3 : Register<"dr3">;
239 def DR4 : Register<"dr4">;
240 def DR5 : Register<"dr5">;
241 def DR6 : Register<"dr6">;
242 def DR7 : Register<"dr7">;
243
244 // Control registers
245 def CR0 : Register<"cr0">;
246 def CR1 : Register<"cr1">;
247 def CR2 : Register<"cr2">;
248 def CR3 : Register<"cr3">;
249 def CR4 : Register<"cr4">;
250 def CR5 : Register<"cr5">;
251 def CR6 : Register<"cr6">;
252 def CR7 : Register<"cr7">;
253 def CR8 : Register<"cr8">;
254 def CR9 : Register<"cr9">;
255 def CR10 : Register<"cr10">;
256 def CR11 : Register<"cr11">;
257 def CR12 : Register<"cr12">;
258 def CR13 : Register<"cr13">;
259 def CR14 : Register<"cr14">;
260 def CR15 : Register<"cr15">;
261
262 // Pseudo index registers
263 def EIZ : Register<"eiz">;
264 def RIZ : Register<"riz">;
265 }
27 def sub_xmm : SubRegIndex;
28 }
29
30 //===----------------------------------------------------------------------===//
31 // Register definitions...
32 //
33
34 // In the register alias definitions below, we define which registers alias
35 // which others. We only specify which registers the small registers alias,
36 // because the register file generator is smart enough to figure out that
37 // AL aliases AX if we tell it that AX aliased AL (for example).
38
39 // Dwarf numbering is different for 32-bit and 64-bit, and there are
40 // variations by target as well. Currently the first entry is for X86-64,
41 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
42 // and debug information on X86-32/Darwin)
43
44 // 8-bit registers
45 // Low registers
46 def AL : X86Reg<"al", 0>;
47 def DL : X86Reg<"dl", 2>;
48 def CL : X86Reg<"cl", 1>;
49 def BL : X86Reg<"bl", 3>;
50
51 // High registers. On x86-64, these cannot be used in any instruction
52 // with a REX prefix.
53 def AH : X86Reg<"ah", 4>;
54 def DH : X86Reg<"dh", 6>;
55 def CH : X86Reg<"ch", 5>;
56 def BH : X86Reg<"bh", 7>;
57
58 // X86-64 only, requires REX.
59 let CostPerUse = 1 in {
60 def SIL : X86Reg<"sil", 6>;
61 def DIL : X86Reg<"dil", 7>;
62 def BPL : X86Reg<"bpl", 5>;
63 def SPL : X86Reg<"spl", 4>;
64 def R8B : X86Reg<"r8b", 8>;
65 def R9B : X86Reg<"r9b", 9>;
66 def R10B : X86Reg<"r10b", 10>;
67 def R11B : X86Reg<"r11b", 11>;
68 def R12B : X86Reg<"r12b", 12>;
69 def R13B : X86Reg<"r13b", 13>;
70 def R14B : X86Reg<"r14b", 14>;
71 def R15B : X86Reg<"r15b", 15>;
72 }
73
74 // 16-bit registers
75 let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
76 def AX : X86Reg<"ax", 0, [AL,AH]>;
77 def DX : X86Reg<"dx", 2, [DL,DH]>;
78 def CX : X86Reg<"cx", 1, [CL,CH]>;
79 def BX : X86Reg<"bx", 3, [BL,BH]>;
80 }
81 let SubRegIndices = [sub_8bit] in {
82 def SI : X86Reg<"si", 6, [SIL]>;
83 def DI : X86Reg<"di", 7, [DIL]>;
84 def BP : X86Reg<"bp", 5, [BPL]>;
85 def SP : X86Reg<"sp", 4, [SPL]>;
86 }
87 def IP : X86Reg<"ip", 0>;
88
89 // X86-64 only, requires REX.
90 let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
91 def R8W : X86Reg<"r8w", 8, [R8B]>;
92 def R9W : X86Reg<"r9w", 9, [R9B]>;
93 def R10W : X86Reg<"r10w", 10, [R10B]>;
94 def R11W : X86Reg<"r11w", 11, [R11B]>;
95 def R12W : X86Reg<"r12w", 12, [R12B]>;
96 def R13W : X86Reg<"r13w", 13, [R13B]>;
97 def R14W : X86Reg<"r14w", 14, [R14B]>;
98 def R15W : X86Reg<"r15w", 15, [R15B]>;
99 }
100
101 // 32-bit registers
102 let SubRegIndices = [sub_16bit] in {
103 def EAX : X86Reg<"eax", 0, [AX]>, DwarfRegNum<[-2, 0, 0]>;
104 def EDX : X86Reg<"edx", 2, [DX]>, DwarfRegNum<[-2, 2, 2]>;
105 def ECX : X86Reg<"ecx", 1, [CX]>, DwarfRegNum<[-2, 1, 1]>;
106 def EBX : X86Reg<"ebx", 3, [BX]>, DwarfRegNum<[-2, 3, 3]>;
107 def ESI : X86Reg<"esi", 6, [SI]>, DwarfRegNum<[-2, 6, 6]>;
108 def EDI : X86Reg<"edi", 7, [DI]>, DwarfRegNum<[-2, 7, 7]>;
109 def EBP : X86Reg<"ebp", 5, [BP]>, DwarfRegNum<[-2, 4, 5]>;
110 def ESP : X86Reg<"esp", 4, [SP]>, DwarfRegNum<[-2, 5, 4]>;
111 def EIP : X86Reg<"eip", 0, [IP]>, DwarfRegNum<[-2, 8, 8]>;
112
113 // X86-64 only, requires REX
114 let CostPerUse = 1 in {
115 def R8D : X86Reg<"r8d", 8, [R8W]>;
116 def R9D : X86Reg<"r9d", 9, [R9W]>;
117 def R10D : X86Reg<"r10d", 10, [R10W]>;
118 def R11D : X86Reg<"r11d", 11, [R11W]>;
119 def R12D : X86Reg<"r12d", 12, [R12W]>;
120 def R13D : X86Reg<"r13d", 13, [R13W]>;
121 def R14D : X86Reg<"r14d", 14, [R14W]>;
122 def R15D : X86Reg<"r15d", 15, [R15W]>;
123 }}
124
125 // 64-bit registers, X86-64 only
126 let SubRegIndices = [sub_32bit] in {
127 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
128 def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
129 def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;
130 def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>;
131 def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>;
132 def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>;
133 def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>;
134 def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
135
136 // These also require REX.
137 let CostPerUse = 1 in {
138 def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>;
139 def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>;
140 def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>;
141 def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>;
142 def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>;
143 def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>;
144 def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>;
145 def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;
146 def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
147 }}
148
149 // MMX Registers. These are actually aliased to ST0 .. ST7
150 def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
151 def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>;
152 def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>;
153 def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;
154 def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;
155 def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>;
156 def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>;
157 def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
158
159 // Pseudo Floating Point registers
160 def FP0 : X86Reg<"fp0", 0>;
161 def FP1 : X86Reg<"fp1", 0>;
162 def FP2 : X86Reg<"fp2", 0>;
163 def FP3 : X86Reg<"fp3", 0>;
164 def FP4 : X86Reg<"fp4", 0>;
165 def FP5 : X86Reg<"fp5", 0>;
166 def FP6 : X86Reg<"fp6", 0>;
167
168 // XMM Registers, used by the various SSE instruction set extensions.
169 def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>;
170 def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>;
171 def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>;
172 def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>;
173 def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>;
174 def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>;
175 def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>;
176 def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>;
177
178 // X86-64 only
179 let CostPerUse = 1 in {
180 def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>;
181 def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>;
182 def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>;
183 def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>;
184 def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>;
185 def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>;
186 def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>;
187 def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>;
188 } // CostPerUse
189
190 // YMM Registers, used by AVX instructions
191 let SubRegIndices = [sub_xmm] in {
192 def YMM0: X86Reg<"ymm0", 0, [XMM0]>, DwarfRegAlias;
193 def YMM1: X86Reg<"ymm1", 1, [XMM1]>, DwarfRegAlias;
194 def YMM2: X86Reg<"ymm2", 2, [XMM2]>, DwarfRegAlias;
195 def YMM3: X86Reg<"ymm3", 3, [XMM3]>, DwarfRegAlias;
196 def YMM4: X86Reg<"ymm4", 4, [XMM4]>, DwarfRegAlias;
197 def YMM5: X86Reg<"ymm5", 5, [XMM5]>, DwarfRegAlias;
198 def YMM6: X86Reg<"ymm6", 6, [XMM6]>, DwarfRegAlias;
199 def YMM7: X86Reg<"ymm7", 7, [XMM7]>, DwarfRegAlias;
200 def YMM8: X86Reg<"ymm8", 8, [XMM8]>, DwarfRegAlias;
201 def YMM9: X86Reg<"ymm9", 9, [XMM9]>, DwarfRegAlias;
202 def YMM10: X86Reg<"ymm10", 10, [XMM10]>, DwarfRegAlias;
203 def YMM11: X86Reg<"ymm11", 11, [XMM11]>, DwarfRegAlias;
204 def YMM12: X86Reg<"ymm12", 12, [XMM12]>, DwarfRegAlias;
205 def YMM13: X86Reg<"ymm13", 13, [XMM13]>, DwarfRegAlias;
206 def YMM14: X86Reg<"ymm14", 14, [XMM14]>, DwarfRegAlias;
207 def YMM15: X86Reg<"ymm15", 15, [XMM15]>, DwarfRegAlias;
208 }
209
210 class STRegister Enc, list A> : X86Reg {
211 let Aliases = A;
212 }
213
214 // Floating point stack registers. These don't map one-to-one to the FP
215 // pseudo registers, but we still mark them as aliasing FP registers. That
216 // way both kinds can be live without exceeding the stack depth. ST registers
217 // are only live around inline assembly.
218 def ST0 : STRegister<"st(0)", 0, []>, DwarfRegNum<[33, 12, 11]>;
219 def ST1 : STRegister<"st(1)", 1, [FP6]>, DwarfRegNum<[34, 13, 12]>;
220 def ST2 : STRegister<"st(2)", 2, [FP5]>, DwarfRegNum<[35, 14, 13]>;
221 def ST3 : STRegister<"st(3)", 3, [FP4]>, DwarfRegNum<[36, 15, 14]>;
222 def ST4 : STRegister<"st(4)", 4, [FP3]>, DwarfRegNum<[37, 16, 15]>;
223 def ST5 : STRegister<"st(5)", 5, [FP2]>, DwarfRegNum<[38, 17, 16]>;
224 def ST6 : STRegister<"st(6)", 6, [FP1]>, DwarfRegNum<[39, 18, 17]>;
225 def ST7 : STRegister<"st(7)", 7, [FP0]>, DwarfRegNum<[40, 19, 18]>;
226
227 // Floating-point status word
228 def FPSW : X86Reg<"fpsw", 0>;
229
230 // Status flags register
231 def EFLAGS : X86Reg<"flags", 0>;
232
233 // Segment registers
234 def CS : X86Reg<"cs", 1>;
235 def DS : X86Reg<"ds", 3>;
236 def SS : X86Reg<"ss", 2>;
237 def ES : X86Reg<"es", 0>;
238 def FS : X86Reg<"fs", 4>;
239 def GS : X86Reg<"gs", 5>;
240
241 // Debug registers
242 def DR0 : X86Reg<"dr0", 0>;
243 def DR1 : X86Reg<"dr1", 1>;
244 def DR2 : X86Reg<"dr2", 2>;
245 def DR3 : X86Reg<"dr3", 3>;
246 def DR4 : X86Reg<"dr4", 4>;
247 def DR5 : X86Reg<"dr5", 5>;
248 def DR6 : X86Reg<"dr6", 6>;
249 def DR7 : X86Reg<"dr7", 7>;
250
251 // Control registers
252 def CR0 : X86Reg<"cr0", 0>;
253 def CR1 : X86Reg<"cr1", 1>;
254 def CR2 : X86Reg<"cr2", 2>;
255 def CR3 : X86Reg<"cr3", 3>;
256 def CR4 : X86Reg<"cr4", 4>;
257 def CR5 : X86Reg<"cr5", 5>;
258 def CR6 : X86Reg<"cr6", 6>;
259 def CR7 : X86Reg<"cr7", 7>;
260 def CR8 : X86Reg<"cr8", 8>;
261 def CR9 : X86Reg<"cr9", 9>;
262 def CR10 : X86Reg<"cr10", 10>;
263 def CR11 : X86Reg<"cr11", 11>;
264 def CR12 : X86Reg<"cr12", 12>;
265 def CR13 : X86Reg<"cr13", 13>;
266 def CR14 : X86Reg<"cr14", 14>;
267 def CR15 : X86Reg<"cr15", 15>;
268
269 // Pseudo index registers
270 def EIZ : X86Reg<"eiz", 4>;
271 def RIZ : X86Reg<"riz", 4>;
266272
267273
268274 //===----------------------------------------------------------------------===//