llvm.org GIT mirror llvm / 7a6cb15
This patch addresses PR13949. For the PowerPC 64-bit ELF Linux ABI, aggregates of size less than 8 bytes are to be passed in the low-order bits ("right-adjusted") of the doubleword register or memory slot assigned to them. A previous patch addressed this for aggregates passed in registers. However, small aggregates passed in the overflow portion of the parameter save area are still being passed left-adjusted. The fix is made in PPCTargetLowering::LowerCall_Darwin_Or_64SVR4 on the caller side, and in PPCTargetLowering::LowerFormalArguments_64SVR4 on the callee side. The main fix on the callee side simply extends existing logic for 1- and 2-byte objects to 1- through 7-byte objects, and correcting a constant left over from 32-bit code. There is also a fix to a bogus calculation of the offset to the following argument in the parameter save area. On the caller side, again a constant left over from 32-bit code is fixed. Additionally, some code for 1, 2, and 4-byte objects is duplicated to handle the 3, 5, 6, and 7-byte objects for SVR4 only. The LowerCall_Darwin_Or_64SVR4 logic is getting fairly convoluted trying to handle both ABIs, and I propose to separate this into two functions in a future patch, at which time the duplication can be removed. The patch adds a new test (structsinmem.ll) to demonstrate correct passing of structures of all seven sizes. Eight dummy parameters are used to force these structures to be in the overflow portion of the parameter save area. As a side effect, this corrects the case when aggregates passed in registers are saved into the first eight doublewords of the parameter save area: Previously they were stored left-justified, and now are properly stored right-justified. This requires changing the expected output of existing test case structsinregs.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166022 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Schmidt 8 years ago
3 changed file(s) with 283 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
20342034 ObjSize = Flags.getByValSize();
20352035 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
20362036 // All aggregates smaller than 8 bytes must be passed right-justified.
2037 if (ObjSize==1 || ObjSize==2) {
2038 CurArgOffset = CurArgOffset + (4 - ObjSize);
2039 }
2037 if (ObjSize < PtrByteSize)
2038 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
20402039 // The value of the object is its address.
20412040 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
20422041 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
20862085 ++GPR_idx;
20872086 ArgOffset += PtrByteSize;
20882087 } else {
2089 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2088 ArgOffset += ArgSize - j;
20902089 break;
20912090 }
20922091 }
36383637
36393638 ArgOffset += PtrByteSize;
36403639 } else {
3641 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3640 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3641 PtrOff.getValueType());
36423642 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
36433643 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
36443644 CallSeqStart.getNode()->getOperand(0),
36453645 Flags, DAG, dl);
3646 // This must go outside the CALLSEQ_START..END.
3646 // The MEMCPY must go outside the CALLSEQ_START..END.
36473647 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
36483648 CallSeqStart.getNode()->getOperand(1));
36493649 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
36513651 Chain = CallSeqStart = NewCallSeqStart;
36523652 ArgOffset += PtrByteSize;
36533653 }
3654 continue;
3655 } else if (isSVR4ABI && GPR_idx == NumGPRs && Size < 8) {
3656 // Case: Size is 3, 5, 6, or 7 for SVR4 and we're out of registers.
3657 // This is the same case as 1, 2, and 4 for SVR4 with no registers.
3658 // FIXME: Separate into 64-bit SVR4 and Darwin versions of this
3659 // function, and combine the duplicated code chunks.
3660 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3661 PtrOff.getValueType());
3662 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3663 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
3664 CallSeqStart.getNode()->getOperand(0),
3665 Flags, DAG, dl);
3666 // The MEMCPY must go outside the CALLSEQ_START..END.
3667 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3668 CallSeqStart.getNode()->getOperand(1));
3669 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3670 NewCallSeqStart.getNode());
3671 Chain = CallSeqStart = NewCallSeqStart;
3672 ArgOffset += PtrByteSize;
36543673 continue;
36553674 }
36563675 // Copy entire object into memory. There are cases where gcc-generated
0 ; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s
1
2 ; FIXME: The code generation for packed structs is very poor because the
3 ; PowerPC target wrongly rejects all unaligned loads. This test case will
4 ; need to be revised when that is fixed.
5
6 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
7 target triple = "powerpc64-unknown-linux-gnu"
8
9 %struct.s1 = type { i8 }
10 %struct.s2 = type { i16 }
11 %struct.s4 = type { i32 }
12 %struct.t1 = type { i8 }
13 %struct.t3 = type <{ i16, i8 }>
14 %struct.t5 = type <{ i32, i8 }>
15 %struct.t6 = type <{ i32, i16 }>
16 %struct.t7 = type <{ i32, i16, i8 }>
17 %struct.s3 = type { i16, i8 }
18 %struct.s5 = type { i32, i8 }
19 %struct.s6 = type { i32, i16 }
20 %struct.s7 = type { i32, i16, i8 }
21 %struct.t2 = type <{ i16 }>
22 %struct.t4 = type <{ i32 }>
23
24 @caller1.p1 = private unnamed_addr constant %struct.s1 { i8 1 }, align 1
25 @caller1.p2 = private unnamed_addr constant %struct.s2 { i16 2 }, align 2
26 @caller1.p3 = private unnamed_addr constant { i16, i8, i8 } { i16 4, i8 8, i8 undef }, align 2
27 @caller1.p4 = private unnamed_addr constant %struct.s4 { i32 16 }, align 4
28 @caller1.p5 = private unnamed_addr constant { i32, i8, [3 x i8] } { i32 32, i8 64, [3 x i8] undef }, align 4
29 @caller1.p6 = private unnamed_addr constant { i32, i16, [2 x i8] } { i32 128, i16 256, [2 x i8] undef }, align 4
30 @caller1.p7 = private unnamed_addr constant { i32, i16, i8, i8 } { i32 512, i16 1024, i8 -3, i8 undef }, align 4
31 @caller2.p1 = private unnamed_addr constant %struct.t1 { i8 1 }, align 1
32 @caller2.p2 = private unnamed_addr constant { i16 } { i16 2 }, align 1
33 @caller2.p3 = private unnamed_addr constant %struct.t3 <{ i16 4, i8 8 }>, align 1
34 @caller2.p4 = private unnamed_addr constant { i32 } { i32 16 }, align 1
35 @caller2.p5 = private unnamed_addr constant %struct.t5 <{ i32 32, i8 64 }>, align 1
36 @caller2.p6 = private unnamed_addr constant %struct.t6 <{ i32 128, i16 256 }>, align 1
37 @caller2.p7 = private unnamed_addr constant %struct.t7 <{ i32 512, i16 1024, i8 -3 }>, align 1
38
39 define i32 @caller1() nounwind {
40 entry:
41 %p1 = alloca %struct.s1, align 1
42 %p2 = alloca %struct.s2, align 2
43 %p3 = alloca %struct.s3, align 2
44 %p4 = alloca %struct.s4, align 4
45 %p5 = alloca %struct.s5, align 4
46 %p6 = alloca %struct.s6, align 4
47 %p7 = alloca %struct.s7, align 4
48 %0 = bitcast %struct.s1* %p1 to i8*
49 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds (%struct.s1* @caller1.p1, i32 0, i32 0), i64 1, i32 1, i1 false)
50 %1 = bitcast %struct.s2* %p2 to i8*
51 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast (%struct.s2* @caller1.p2 to i8*), i64 2, i32 2, i1 false)
52 %2 = bitcast %struct.s3* %p3 to i8*
53 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* bitcast ({ i16, i8, i8 }* @caller1.p3 to i8*), i64 4, i32 2, i1 false)
54 %3 = bitcast %struct.s4* %p4 to i8*
55 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %3, i8* bitcast (%struct.s4* @caller1.p4 to i8*), i64 4, i32 4, i1 false)
56 %4 = bitcast %struct.s5* %p5 to i8*
57 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %4, i8* bitcast ({ i32, i8, [3 x i8] }* @caller1.p5 to i8*), i64 8, i32 4, i1 false)
58 %5 = bitcast %struct.s6* %p6 to i8*
59 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %5, i8* bitcast ({ i32, i16, [2 x i8] }* @caller1.p6 to i8*), i64 8, i32 4, i1 false)
60 %6 = bitcast %struct.s7* %p7 to i8*
61 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %6, i8* bitcast ({ i32, i16, i8, i8 }* @caller1.p7 to i8*), i64 8, i32 4, i1 false)
62 %call = call i32 @callee1(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, %struct.s1* byval %p1, %struct.s2* byval %p2, %struct.s3* byval %p3, %struct.s4* byval %p4, %struct.s5* byval %p5, %struct.s6* byval %p6, %struct.s7* byval %p7)
63 ret i32 %call
64
65 ; CHECK: stb {{[0-9]+}}, 119(1)
66 ; CHECK: sth {{[0-9]+}}, 126(1)
67 ; CHECK: stw {{[0-9]+}}, 132(1)
68 ; CHECK: stw {{[0-9]+}}, 140(1)
69 ; CHECK: std {{[0-9]+}}, 144(1)
70 ; CHECK: std {{[0-9]+}}, 152(1)
71 ; CHECK: std {{[0-9]+}}, 160(1)
72 }
73
74 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
75
76 define internal i32 @callee1(i32 %z1, i32 %z2, i32 %z3, i32 %z4, i32 %z5, i32 %z6, i32 %z7, i32 %z8, %struct.s1* byval %v1, %struct.s2* byval %v2, %struct.s3* byval %v3, %struct.s4* byval %v4, %struct.s5* byval %v5, %struct.s6* byval %v6, %struct.s7* byval %v7) nounwind {
77 entry:
78 %z1.addr = alloca i32, align 4
79 %z2.addr = alloca i32, align 4
80 %z3.addr = alloca i32, align 4
81 %z4.addr = alloca i32, align 4
82 %z5.addr = alloca i32, align 4
83 %z6.addr = alloca i32, align 4
84 %z7.addr = alloca i32, align 4
85 %z8.addr = alloca i32, align 4
86 store i32 %z1, i32* %z1.addr, align 4
87 store i32 %z2, i32* %z2.addr, align 4
88 store i32 %z3, i32* %z3.addr, align 4
89 store i32 %z4, i32* %z4.addr, align 4
90 store i32 %z5, i32* %z5.addr, align 4
91 store i32 %z6, i32* %z6.addr, align 4
92 store i32 %z7, i32* %z7.addr, align 4
93 store i32 %z8, i32* %z8.addr, align 4
94 %a = getelementptr inbounds %struct.s1* %v1, i32 0, i32 0
95 %0 = load i8* %a, align 1
96 %conv = zext i8 %0 to i32
97 %a1 = getelementptr inbounds %struct.s2* %v2, i32 0, i32 0
98 %1 = load i16* %a1, align 2
99 %conv2 = sext i16 %1 to i32
100 %add = add nsw i32 %conv, %conv2
101 %a3 = getelementptr inbounds %struct.s3* %v3, i32 0, i32 0
102 %2 = load i16* %a3, align 2
103 %conv4 = sext i16 %2 to i32
104 %add5 = add nsw i32 %add, %conv4
105 %a6 = getelementptr inbounds %struct.s4* %v4, i32 0, i32 0
106 %3 = load i32* %a6, align 4
107 %add7 = add nsw i32 %add5, %3
108 %a8 = getelementptr inbounds %struct.s5* %v5, i32 0, i32 0
109 %4 = load i32* %a8, align 4
110 %add9 = add nsw i32 %add7, %4
111 %a10 = getelementptr inbounds %struct.s6* %v6, i32 0, i32 0
112 %5 = load i32* %a10, align 4
113 %add11 = add nsw i32 %add9, %5
114 %a12 = getelementptr inbounds %struct.s7* %v7, i32 0, i32 0
115 %6 = load i32* %a12, align 4
116 %add13 = add nsw i32 %add11, %6
117 ret i32 %add13
118
119 ; CHECK: lha {{[0-9]+}}, 126(1)
120 ; CHECK: lbz {{[0-9]+}}, 119(1)
121 ; CHECK: lha {{[0-9]+}}, 132(1)
122 ; CHECK: lwz {{[0-9]+}}, 140(1)
123 ; CHECK: lwz {{[0-9]+}}, 144(1)
124 ; CHECK: lwz {{[0-9]+}}, 152(1)
125 ; CHECK: lwz {{[0-9]+}}, 160(1)
126 }
127
128 define i32 @caller2() nounwind {
129 entry:
130 %p1 = alloca %struct.t1, align 1
131 %p2 = alloca %struct.t2, align 1
132 %p3 = alloca %struct.t3, align 1
133 %p4 = alloca %struct.t4, align 1
134 %p5 = alloca %struct.t5, align 1
135 %p6 = alloca %struct.t6, align 1
136 %p7 = alloca %struct.t7, align 1
137 %0 = bitcast %struct.t1* %p1 to i8*
138 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* getelementptr inbounds (%struct.t1* @caller2.p1, i32 0, i32 0), i64 1, i32 1, i1 false)
139 %1 = bitcast %struct.t2* %p2 to i8*
140 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ({ i16 }* @caller2.p2 to i8*), i64 2, i32 1, i1 false)
141 %2 = bitcast %struct.t3* %p3 to i8*
142 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* bitcast (%struct.t3* @caller2.p3 to i8*), i64 3, i32 1, i1 false)
143 %3 = bitcast %struct.t4* %p4 to i8*
144 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %3, i8* bitcast ({ i32 }* @caller2.p4 to i8*), i64 4, i32 1, i1 false)
145 %4 = bitcast %struct.t5* %p5 to i8*
146 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %4, i8* bitcast (%struct.t5* @caller2.p5 to i8*), i64 5, i32 1, i1 false)
147 %5 = bitcast %struct.t6* %p6 to i8*
148 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %5, i8* bitcast (%struct.t6* @caller2.p6 to i8*), i64 6, i32 1, i1 false)
149 %6 = bitcast %struct.t7* %p7 to i8*
150 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %6, i8* bitcast (%struct.t7* @caller2.p7 to i8*), i64 7, i32 1, i1 false)
151 %call = call i32 @callee2(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, %struct.t1* byval %p1, %struct.t2* byval %p2, %struct.t3* byval %p3, %struct.t4* byval %p4, %struct.t5* byval %p5, %struct.t6* byval %p6, %struct.t7* byval %p7)
152 ret i32 %call
153
154 ; CHECK: stb {{[0-9]+}}, 119(1)
155 ; CHECK: sth {{[0-9]+}}, 126(1)
156 ; CHECK: stb {{[0-9]+}}, 135(1)
157 ; CHECK: sth {{[0-9]+}}, 133(1)
158 ; CHECK: stw {{[0-9]+}}, 140(1)
159 ; CHECK: stb {{[0-9]+}}, 151(1)
160 ; CHECK: stw {{[0-9]+}}, 147(1)
161 ; CHECK: sth {{[0-9]+}}, 158(1)
162 ; CHECK: stw {{[0-9]+}}, 154(1)
163 ; CHECK: stb {{[0-9]+}}, 167(1)
164 ; CHECK: sth {{[0-9]+}}, 165(1)
165 ; CHECK: stw {{[0-9]+}}, 161(1)
166 }
167
168 define internal i32 @callee2(i32 %z1, i32 %z2, i32 %z3, i32 %z4, i32 %z5, i32 %z6, i32 %z7, i32 %z8, %struct.t1* byval %v1, %struct.t2* byval %v2, %struct.t3* byval %v3, %struct.t4* byval %v4, %struct.t5* byval %v5, %struct.t6* byval %v6, %struct.t7* byval %v7) nounwind {
169 entry:
170 %z1.addr = alloca i32, align 4
171 %z2.addr = alloca i32, align 4
172 %z3.addr = alloca i32, align 4
173 %z4.addr = alloca i32, align 4
174 %z5.addr = alloca i32, align 4
175 %z6.addr = alloca i32, align 4
176 %z7.addr = alloca i32, align 4
177 %z8.addr = alloca i32, align 4
178 store i32 %z1, i32* %z1.addr, align 4
179 store i32 %z2, i32* %z2.addr, align 4
180 store i32 %z3, i32* %z3.addr, align 4
181 store i32 %z4, i32* %z4.addr, align 4
182 store i32 %z5, i32* %z5.addr, align 4
183 store i32 %z6, i32* %z6.addr, align 4
184 store i32 %z7, i32* %z7.addr, align 4
185 store i32 %z8, i32* %z8.addr, align 4
186 %a = getelementptr inbounds %struct.t1* %v1, i32 0, i32 0
187 %0 = load i8* %a, align 1
188 %conv = zext i8 %0 to i32
189 %a1 = getelementptr inbounds %struct.t2* %v2, i32 0, i32 0
190 %1 = load i16* %a1, align 1
191 %conv2 = sext i16 %1 to i32
192 %add = add nsw i32 %conv, %conv2
193 %a3 = getelementptr inbounds %struct.t3* %v3, i32 0, i32 0
194 %2 = load i16* %a3, align 1
195 %conv4 = sext i16 %2 to i32
196 %add5 = add nsw i32 %add, %conv4
197 %a6 = getelementptr inbounds %struct.t4* %v4, i32 0, i32 0
198 %3 = load i32* %a6, align 1
199 %add7 = add nsw i32 %add5, %3
200 %a8 = getelementptr inbounds %struct.t5* %v5, i32 0, i32 0
201 %4 = load i32* %a8, align 1
202 %add9 = add nsw i32 %add7, %4
203 %a10 = getelementptr inbounds %struct.t6* %v6, i32 0, i32 0
204 %5 = load i32* %a10, align 1
205 %add11 = add nsw i32 %add9, %5
206 %a12 = getelementptr inbounds %struct.t7* %v7, i32 0, i32 0
207 %6 = load i32* %a12, align 1
208 %add13 = add nsw i32 %add11, %6
209 ret i32 %add13
210
211 ; CHECK: lbz {{[0-9]+}}, 149(1)
212 ; CHECK: lbz {{[0-9]+}}, 150(1)
213 ; CHECK: lbz {{[0-9]+}}, 147(1)
214 ; CHECK: lbz {{[0-9]+}}, 148(1)
215 ; CHECK: lbz {{[0-9]+}}, 133(1)
216 ; CHECK: lbz {{[0-9]+}}, 134(1)
217 ; CHECK: lha {{[0-9]+}}, 126(1)
218 ; CHECK: lbz {{[0-9]+}}, 119(1)
219 ; CHECK: lwz {{[0-9]+}}, 140(1)
220 ; CHECK: lhz {{[0-9]+}}, 154(1)
221 ; CHECK: lhz {{[0-9]+}}, 156(1)
222 ; CHECK: lbz {{[0-9]+}}, 163(1)
223 ; CHECK: lbz {{[0-9]+}}, 164(1)
224 ; CHECK: lbz {{[0-9]+}}, 161(1)
225 ; CHECK: lbz {{[0-9]+}}, 162(1)
226 }
0 ; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s
1
2 ; FIXME: The code generation for packed structs is very poor because the
3 ; PowerPC target wrongly rejects all unaligned loads. This test case will
4 ; need to be revised when that is fixed.
15
26 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
37 target triple = "powerpc64-unknown-linux-gnu"
99103 ; CHECK: std 9, 96(1)
100104 ; CHECK: std 8, 88(1)
101105 ; CHECK: std 7, 80(1)
102 ; CHECK: stw 6, 72(1)
103 ; CHECK: stw 5, 64(1)
104 ; CHECK: sth 4, 58(1)
105 ; CHECK: stb 3, 51(1)
106 ; CHECK: lha {{[0-9]+}}, 58(1)
107 ; CHECK: lbz {{[0-9]+}}, 51(1)
108 ; CHECK: lha {{[0-9]+}}, 64(1)
109 ; CHECK: lwz {{[0-9]+}}, 72(1)
106 ; CHECK: stw 6, 76(1)
107 ; CHECK: stw 5, 68(1)
108 ; CHECK: sth 4, 62(1)
109 ; CHECK: stb 3, 55(1)
110 ; CHECK: lha {{[0-9]+}}, 62(1)
111 ; CHECK: lbz {{[0-9]+}}, 55(1)
112 ; CHECK: lha {{[0-9]+}}, 68(1)
113 ; CHECK: lwz {{[0-9]+}}, 76(1)
110114 ; CHECK: lwz {{[0-9]+}}, 80(1)
111115 ; CHECK: lwz {{[0-9]+}}, 88(1)
112116 ; CHECK: lwz {{[0-9]+}}, 96(1)
187191 ; CHECK: sldi 8, 8, 16
188192 ; CHECK: sldi 7, 7, 24
189193 ; CHECK: sldi 5, 5, 40
190 ; CHECK: stw 6, 72(1)
191 ; CHECK: sth 4, 58(1)
192 ; CHECK: stb 3, 51(1)
194 ; CHECK: stw 6, 76(1)
195 ; CHECK: sth 4, 62(1)
196 ; CHECK: stb 3, 55(1)
193197 ; CHECK: std 9, 96(1)
194198 ; CHECK: std 8, 88(1)
195199 ; CHECK: std 7, 80(1)
196200 ; CHECK: std 5, 64(1)
197 ; CHECK: lha {{[0-9]+}}, 58(1)
198 ; CHECK: lbz {{[0-9]+}}, 51(1)
199 ; CHECK: lha {{[0-9]+}}, 64(1)
200 ; CHECK: lwz {{[0-9]+}}, 72(1)
201 ; CHECK: lwz {{[0-9]+}}, 80(1)
202 ; CHECK: lwz {{[0-9]+}}, 88(1)
203 ; CHECK: lwz {{[0-9]+}}, 96(1)
204 }
201 ; CHECK: lbz {{[0-9]+}}, 85(1)
202 ; CHECK: lbz {{[0-9]+}}, 86(1)
203 ; CHECK: lbz {{[0-9]+}}, 83(1)
204 ; CHECK: lbz {{[0-9]+}}, 84(1)
205 ; CHECK: lbz {{[0-9]+}}, 69(1)
206 ; CHECK: lbz {{[0-9]+}}, 70(1)
207 ; CHECK: lha {{[0-9]+}}, 62(1)
208 ; CHECK: lbz {{[0-9]+}}, 55(1)
209 ; CHECK: lwz {{[0-9]+}}, 76(1)
210 ; CHECK: lhz {{[0-9]+}}, 90(1)
211 ; CHECK: lhz {{[0-9]+}}, 92(1)
212 ; CHECK: lbz {{[0-9]+}}, 99(1)
213 ; CHECK: lbz {{[0-9]+}}, 100(1)
214 ; CHECK: lbz {{[0-9]+}}, 97(1)
215 ; CHECK: lbz {{[0-9]+}}, 98(1)
216 }