llvm.org GIT mirror llvm / 7a4708e
Adjust ScheduleDAGSDNodes::RegDefIter for patchpoints PATCHPOINT is a strange pseudo-instruction. Depending on how it is used, and whether or not the AnyReg calling convention is being used, it might or might not define a value. However, its TableGen definition says that it defines one value, and so when it doesn't, the code in ScheduleDAGSDNodes::RegDefIter becomes confused and the code that uses the RegDefIter will try to get the register class of the MVT::Other type associated with the PATCHPOINT's chain result (under certain circumstances). This will be covered by the PPC64 PatchPoint test cases once that support is re-committed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225907 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 5 years ago
1 changed file(s) with 8 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
547547 unsigned POpc = Node->getMachineOpcode();
548548 if (POpc == TargetOpcode::IMPLICIT_DEF) {
549549 // No register need be allocated for this.
550 NodeNumDefs = 0;
551 return;
552 }
553 if (POpc == TargetOpcode::PATCHPOINT &&
554 Node->getValueType(0) == MVT::Other) {
555 // PATCHPOINT is defined to have one result, but it might really have none
556 // if we're not using CallingConv::AnyReg. Don't mistake the chain for a
557 // real definition.
550558 NodeNumDefs = 0;
551559 return;
552560 }