llvm.org GIT mirror llvm / 7a15273
Describe how the JIT maps fields to MachineOperands, patch by JP Bonn! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59876 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 10 years ago
1 changed file(s) with 83 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
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  • Instruction Set
  • 3030
    31
  • Instruction Operand Mapping
  • 3132
  • Implement a subclass of TargetInstrInfo
  • 3233
  • Branch Folding and If Conversion
  • 3334
    997998
    998999
    9991000
    1001 Instruction Operand Mapping
    1002
    1003
    1004

    The code generator backend maps instruction operands to fields in

    1005 the instruction. Operands are assigned to unbound fields in the instruction in
    1006 the order they are defined. Fields are bound when they are assigned a value.
    1007 For example, the Sparc target defines the XNORrr instruction as a F3_1 format
    1008 instruction having three operands.

    1009
    1010
    1011
    
                      
                    
    1012 def XNORrr : F3_1<2, 0b000111,
    1013 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
    1014 "xnor $b, $c, $dst",
    1015 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
    1016
    1017
    1018
    1019

    The instruction templates in SparcInstrFormats.td show the base class for F3_1 is InstSP.

    1020
    1021
    1022
    
                      
                    
    1023 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
    1024 field bits<32> Inst;
    1025 let Namespace = "SP";
    1026 bits<2> op;
    1027 let Inst{31-30} = op;
    1028 dag OutOperandList = outs;
    1029 dag InOperandList = ins;
    1030 let AsmString = asmstr;
    1031 let Pattern = pattern;
    1032 }
    1033
    1034
    1035

    1036 InstSP leaves the op field unbound.
    1037

    1038
    1039
    1040
    
                      
                    
    1041 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
    1042 : InstSP<outs, ins, asmstr, pattern> {
    1043 bits<5> rd;
    1044 bits<6> op3;
    1045 bits<5> rs1;
    1046 let op{1} = 1; // Op = 2 or 3
    1047 let Inst{29-25} = rd;
    1048 let Inst{24-19} = op3;
    1049 let Inst{18-14} = rs1;
    1050 }
    1051
    1052
    1053

    1054 F3 binds the op field and defines the rd, op3, and rs1 fields. F3 format instructions will
    1055 bind the operands rd, op3, and rs1 fields.
    1056

    1057
    1058
    1059
    
                      
                    
    1060 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
    1061 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
    1062 bits<8> asi = 0; // asi not currently used
    1063 bits<5> rs2;
    1064 let op = opVal;
    1065 let op3 = op3val;
    1066 let Inst{13} = 0; // i field = 0
    1067 let Inst{12-5} = asi; // address space identifier
    1068 let Inst{4-0} = rs2;
    1069 }
    1070
    1071
    1072

    1073 F3_1 binds the op3 field and defines the rs2 fields. F3_1 format instructions will
    1074 bind the operands to the rd, rs1, and rs2 fields. This results in the XNORrr instruction
    1075 binding $dst, $b, and $c operands to the rd, rs1, and rs2 fields respectively.
    1076

    1077
    1078
    1079
    1080
    1081
    1082
    10001083 Implement a subclass of
    10011084 TargetInstrInfo
    10021085