llvm.org GIT mirror llvm / 79fc6f4
Add a pre-regalloc tail duplication pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90567 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
3 changed file(s) with 228 addition(s) and 101 deletion(s). Raw diff Collapse all Expand all
130130
131131 /// TailDuplicate Pass - Duplicate blocks with unconditional branches
132132 /// into tails of their predecessors.
133 FunctionPass *createTailDuplicatePass();
133 FunctionPass *createTailDuplicatePass(bool PreRegAlloc = false);
134134
135135 /// IfConverter Pass - This pass performs machine code if conversion.
136136 FunctionPass *createIfConverterPass();
7373 static cl::opt EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
7474 cl::desc("Split GEPs and run no-load GVN"));
7575
76 static cl::opt PreAllocTailDup("pre-regalloc-taildup", cl::Hidden,
77 cl::desc("Pre-register allocation tail duplication"));
78
7679 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
7780 const std::string &TargetTriple)
7881 : TargetMachine(T) {
301304 /* allowDoubleDefs= */ true);
302305 }
303306
307 // Pre-ra tail duplication.
308 if (OptLevel != CodeGenOpt::None &&
309 !DisableTailDuplicate && PreAllocTailDup) {
310 PM.add(createTailDuplicatePass(true));
311 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
312 }
313
304314 // Run pre-ra passes.
305315 if (addPreRegAlloc(PM, OptLevel))
306316 printAndVerify(PM, "After PreRegAlloc passes",
347357
348358 // Tail duplication.
349359 if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
350 PM.add(createTailDuplicatePass());
360 PM.add(createTailDuplicatePass(false));
351361 printAndVerify(PM, "After TailDuplicate");
352362 }
353363
4242 namespace {
4343 /// TailDuplicatePass - Perform tail duplication.
4444 class TailDuplicatePass : public MachineFunctionPass {
45 bool PreRegAlloc;
4546 const TargetInstrInfo *TII;
4647 MachineModuleInfo *MMI;
4748 MachineRegisterInfo *MRI;
5556
5657 public:
5758 static char ID;
58 explicit TailDuplicatePass() : MachineFunctionPass(&ID) {}
59 explicit TailDuplicatePass(bool PreRA) :
60 MachineFunctionPass(&ID), PreRegAlloc(PreRA) {}
5961
6062 virtual bool runOnMachineFunction(MachineFunction &MF);
6163 virtual const char *getPassName() const { return "Tail Duplication"; }
6264
6365 private:
6466 void AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg);
67 void ProcessPHI(MachineInstr *MI, MachineBasicBlock *TailBB,
68 MachineBasicBlock *PredBB,
69 DenseMap &LocalVRMap);
70 void DuplicateInstruction(MachineInstr *MI,
71 MachineBasicBlock *TailBB,
72 MachineBasicBlock *PredBB,
73 MachineFunction &MF,
74 DenseMap &LocalVRMap);
75 void UpdateSuccessorsPHIs(MachineBasicBlock *FromBB,MachineBasicBlock *ToBB,
76 SmallSetVector &Succs);
6577 bool TailDuplicateBlocks(MachineFunction &MF);
6678 bool TailDuplicate(MachineBasicBlock *TailBB, MachineFunction &MF);
6779 void RemoveDeadBlock(MachineBasicBlock *MBB);
7082 char TailDuplicatePass::ID = 0;
7183 }
7284
73 FunctionPass *llvm::createTailDuplicatePass() {
74 return new TailDuplicatePass();
85 FunctionPass *llvm::createTailDuplicatePass(bool PreRegAlloc) {
86 return new TailDuplicatePass(PreRegAlloc);
7587 }
7688
7789 bool TailDuplicatePass::runOnMachineFunction(MachineFunction &MF) {
96108 bool TailDuplicatePass::TailDuplicateBlocks(MachineFunction &MF) {
97109 bool MadeChange = false;
98110
99 SSAUpdateVRs.clear();
100 SSAUpdateVals.clear();
101
102111 for (MachineFunction::iterator I = ++MF.begin(), E = MF.end(); I != E; ) {
103112 MachineBasicBlock *MBB = I++;
104113
108117
109118 MadeChange |= TailDuplicate(MBB, MF);
110119
111 // If it is dead, remove it.
112 if (MBB->pred_empty()) {
120 // If it is dead, remove it. Don't do this if this pass is run before
121 // register allocation to avoid having to update PHI nodes.
122 if (!PreRegAlloc && MBB->pred_empty()) {
113123 NumInstrDups -= MBB->size();
114124 RemoveDeadBlock(MBB);
115125 MadeChange = true;
116126 ++NumDeadBlocks;
117 }
118 }
119
120 if (!SSAUpdateVRs.empty()) {
121 // Update SSA form.
122 MachineSSAUpdater SSAUpdate(MF);
123
124 for (unsigned i = 0, e = SSAUpdateVRs.size(); i != e; ++i) {
125 unsigned VReg = SSAUpdateVRs[i];
126 SSAUpdate.Initialize(VReg);
127
128 // If the original definition is still around, add it as an available
129 // value.
130 MachineInstr *DefMI = MRI->getVRegDef(VReg);
131 MachineBasicBlock *DefBB = 0;
132 if (DefMI) {
133 DefBB = DefMI->getParent();
134 SSAUpdate.AddAvailableValue(DefBB, VReg);
135 }
136
137 // Add the new vregs as available values.
138 DenseMap::iterator LI =
139 SSAUpdateVals.find(VReg);
140 for (unsigned j = 0, ee = LI->second.size(); j != ee; ++j) {
141 unsigned NewReg = LI->second[j];
142 MachineInstr *DefMI = MRI->getVRegDef(NewReg);
143 SSAUpdate.AddAvailableValue(DefMI->getParent(), NewReg);
144 }
145
146 // Rewrite uses that are outside of the original def's block.
147 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg),
148 UE = MRI->use_end(); UI != UE; ++UI) {
149 MachineInstr *UseMI = &*UI;
150 if (UseMI->getParent() != DefBB)
151 SSAUpdate.RewriteUse(UI.getOperand());
152 }
153127 }
154128 }
155129
186160 Vals.push_back(NewReg);
187161 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals));
188162 SSAUpdateVRs.push_back(OrigReg);
163 }
164 }
165
166 /// ProcessPHI - Process but do not duplicate a PHI node in TailBB. Remember the
167 /// source register that's contributed by PredBB and update SSA update map.
168 void TailDuplicatePass::ProcessPHI(MachineInstr *MI,
169 MachineBasicBlock *TailBB,
170 MachineBasicBlock *PredBB,
171 DenseMap &LocalVRMap) {
172 unsigned DefReg = MI->getOperand(0).getReg();
173 unsigned SrcOpIdx = getPHISrcRegOpIdx(MI, PredBB);
174 assert(SrcOpIdx && "Unable to find matching PHI source?");
175 unsigned SrcReg = MI->getOperand(SrcOpIdx).getReg();
176 LocalVRMap.insert(std::make_pair(DefReg, SrcReg));
177 if (isDefLiveOut(DefReg, TailBB, MRI))
178 AddSSAUpdateEntry(DefReg, SrcReg);
179
180 // Remove PredBB from the PHI node.
181 MI->RemoveOperand(SrcOpIdx+1);
182 MI->RemoveOperand(SrcOpIdx);
183 if (MI->getNumOperands() == 1)
184 MI->eraseFromParent();
185 }
186
187 /// DuplicateInstruction - Duplicate a TailBB instruction to PredBB and update
188 /// the source operands due to earlier PHI translation.
189 void TailDuplicatePass::DuplicateInstruction(MachineInstr *MI,
190 MachineBasicBlock *TailBB,
191 MachineBasicBlock *PredBB,
192 MachineFunction &MF,
193 DenseMap &LocalVRMap) {
194 MachineInstr *NewMI = MF.CloneMachineInstr(MI);
195 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
196 MachineOperand &MO = NewMI->getOperand(i);
197 if (!MO.isReg())
198 continue;
199 unsigned Reg = MO.getReg();
200 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
201 continue;
202 if (MO.isDef()) {
203 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
204 unsigned NewReg = MRI->createVirtualRegister(RC);
205 MO.setReg(NewReg);
206 LocalVRMap.insert(std::make_pair(Reg, NewReg));
207 if (isDefLiveOut(Reg, TailBB, MRI))
208 AddSSAUpdateEntry(Reg, NewReg);
209 } else {
210 DenseMap::iterator VI = LocalVRMap.find(Reg);
211 if (VI != LocalVRMap.end())
212 MO.setReg(VI->second);
213 }
214 }
215 PredBB->insert(PredBB->end(), NewMI);
216 }
217
218 /// UpdateSuccessorsPHIs - After FromBB is tail duplicated into its predecessor
219 /// blocks, the successors have gained new predecessors. Update the PHI
220 /// instructions in them accordingly.
221 void TailDuplicatePass::UpdateSuccessorsPHIs(MachineBasicBlock *FromBB,
222 MachineBasicBlock *ToBB,
223 SmallSetVector &Succs) {
224 for (SmallSetVector::iterator SI = Succs.begin(),
225 SE = Succs.end(); SI != SE; ++SI) {
226 MachineBasicBlock *SuccBB = *SI;
227 for (MachineBasicBlock::iterator II = SuccBB->begin(), EE = SuccBB->end();
228 II != EE; ++II) {
229 if (II->getOpcode() != TargetInstrInfo::PHI)
230 break;
231 for (unsigned i = 1, e = II->getNumOperands(); i != e; i += 2) {
232 MachineOperand &MO1 = II->getOperand(i+1);
233 if (MO1.getMBB() != FromBB)
234 continue;
235 MachineOperand &MO0 = II->getOperand(i);
236 unsigned Reg = MO0.getReg();
237 if (ToBB) {
238 // Folded into the previous BB.
239 II->RemoveOperand(i+1);
240 II->RemoveOperand(i);
241 }
242 DenseMap::iterator LI =
243 SSAUpdateVals.find(Reg);
244 if (LI == SSAUpdateVals.end())
245 break;
246 for (unsigned j = 0, ee = LI->second.size(); j != ee; ++j) {
247 unsigned NewReg = LI->second[j];
248 MachineInstr *DefMI = MRI->getVRegDef(NewReg);
249 II->addOperand(MachineOperand::CreateReg(NewReg, false));
250 II->addOperand(MachineOperand::CreateMBB(DefMI->getParent()));
251 }
252 break;
253 }
254 }
189255 }
190256 }
191257
221287 I != TailBB->end(); ++I) {
222288 // Non-duplicable things shouldn't be tail-duplicated.
223289 if (I->getDesc().isNotDuplicable()) return false;
290 // Do not duplicate 'return' instructions if this is a pre-regalloc run.
291 // A return may expand into a lot more instructions (e.g. reload of callee
292 // saved registers) after PEI.
293 if (PreRegAlloc && I->getDesc().isReturn()) return false;
224294 // Don't duplicate more than the threshold.
225295 if (InstrCount == MaxDuplicateCount) return false;
226296 // Remember if we saw a call.
237307 // block into them, if possible. Copying the list ahead of time also
238308 // avoids trouble with the predecessor list reallocating.
239309 bool Changed = false;
240 SmallSetVector Preds(TailBB->pred_begin(),
241 TailBB->pred_end());
310 SmallSetVector Preds(TailBB->pred_begin(),
311 TailBB->pred_end());
242312 for (SmallSetVector::iterator PI = Preds.begin(),
243313 PE = Preds.end(); PI != PE; ++PI) {
244314 MachineBasicBlock *PredBB = *PI;
269339 // Clone the contents of TailBB into PredBB.
270340 DenseMap LocalVRMap;
271341 MachineBasicBlock::iterator I = TailBB->begin();
272 MachineBasicBlock::iterator NI;
273 for (MachineBasicBlock::iterator E = TailBB->end(); I != E; I = NI) {
274 NI = next(I);
275 if (I->getOpcode() == TargetInstrInfo::PHI) {
342 while (I != TailBB->end()) {
343 MachineInstr *MI = &*I;
344 ++I;
345 if (MI->getOpcode() == TargetInstrInfo::PHI) {
276346 // Replace the uses of the def of the PHI with the register coming
277347 // from PredBB.
278 unsigned DefReg = I->getOperand(0).getReg();
279 unsigned SrcOpIdx = getPHISrcRegOpIdx(I, PredBB);
280 unsigned SrcReg = I->getOperand(SrcOpIdx).getReg();
281 LocalVRMap.insert(std::make_pair(DefReg, SrcReg));
282 if (isDefLiveOut(DefReg, TailBB, MRI))
283 AddSSAUpdateEntry(DefReg, SrcReg);
284
285 // Remove PredBB from the PHI node.
286 I->RemoveOperand(SrcOpIdx+1);
287 I->RemoveOperand(SrcOpIdx);
288 if (I->getNumOperands() == 1)
289 I->eraseFromParent();
290 continue;
291 }
292
293 // Replace def of virtual registers with new registers, and update uses
294 // with PHI source register or the new registers.
295 MachineInstr *NewMI = MF.CloneMachineInstr(I);
296 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
297 MachineOperand &MO = NewMI->getOperand(i);
298 if (!MO.isReg())
299 continue;
300 unsigned Reg = MO.getReg();
301 if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
302 continue;
303 if (MO.isDef()) {
304 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
305 unsigned NewReg = MRI->createVirtualRegister(RC);
306 MO.setReg(NewReg);
307 LocalVRMap.insert(std::make_pair(Reg, NewReg));
308 if (isDefLiveOut(Reg, TailBB, MRI))
309 AddSSAUpdateEntry(Reg, NewReg);
310 } else {
311 DenseMap::iterator VI = LocalVRMap.find(Reg);
312 if (VI != LocalVRMap.end())
313 MO.setReg(VI->second);
314 }
315 }
316 PredBB->insert(PredBB->end(), NewMI);
348 ProcessPHI(MI, TailBB, PredBB, LocalVRMap);
349 } else {
350 // Replace def of virtual registers with new registers, and update
351 // uses with PHI source register or the new registers.
352 DuplicateInstruction(MI, TailBB, PredBB, MF, LocalVRMap);
353 }
317354 }
318355 NumInstrDups += TailBB->size() - 1; // subtract one for removed branch
319356
322359 assert(PredBB->succ_empty() &&
323360 "TailDuplicate called on block with multiple successors!");
324361 for (MachineBasicBlock::succ_iterator I = TailBB->succ_begin(),
325 E = TailBB->succ_end(); I != E; ++I)
326 PredBB->addSuccessor(*I);
362 E = TailBB->succ_end(); I != E; ++I)
363 PredBB->addSuccessor(*I);
327364
328365 Changed = true;
329366 ++NumTailDups;
330367 }
368
369 // Save the successors list.
370 SmallSetVector Succs(TailBB->succ_begin(),
371 TailBB->succ_end());
331372
332373 // If TailBB was duplicated into all its predecessors except for the prior
333374 // block, which falls through unconditionally, move the contents of this
334375 // block into the prior block.
335 MachineBasicBlock &PrevBB = *prior(MachineFunction::iterator(TailBB));
376 MachineBasicBlock *PrevBB = prior(MachineFunction::iterator(TailBB));
336377 MachineBasicBlock *PriorTBB = 0, *PriorFBB = 0;
337378 SmallVector PriorCond;
338379 bool PriorUnAnalyzable =
339 TII->AnalyzeBranch(PrevBB, PriorTBB, PriorFBB, PriorCond, true);
380 TII->AnalyzeBranch(*PrevBB, PriorTBB, PriorFBB, PriorCond, true);
340381 // This has to check PrevBB->succ_size() because EH edges are ignored by
341382 // AnalyzeBranch.
383 // If TailBB starts with PHIs, then don't bother. Let the post regalloc
384 // run clean it up.
385 MachineBasicBlock *NewTailBB = 0;
342386 if (!PriorUnAnalyzable && PriorCond.empty() && !PriorTBB &&
343 TailBB->pred_size() == 1 && PrevBB.succ_size() == 1 &&
387 TailBB->pred_size() == 1 && PrevBB->succ_size() == 1 &&
344388 !TailBB->hasAddressTaken()) {
345 DEBUG(errs() << "\nMerging into block: " << PrevBB
389 DEBUG(errs() << "\nMerging into block: " << *PrevBB
346390 << "From MBB: " << *TailBB);
347 PrevBB.splice(PrevBB.end(), TailBB, TailBB->begin(), TailBB->end());
348 PrevBB.removeSuccessor(PrevBB.succ_begin());;
349 assert(PrevBB.succ_empty());
350 PrevBB.transferSuccessors(TailBB);
391 if (PreRegAlloc) {
392 DenseMap LocalVRMap;
393 MachineBasicBlock::iterator I = TailBB->begin();
394 // Process PHI instructions first.
395 while (I != TailBB->end() && I->getOpcode() == TargetInstrInfo::PHI) {
396 // Replace the uses of the def of the PHI with the register coming
397 // from PredBB.
398 MachineInstr *MI = &*I++;
399 ProcessPHI(MI, TailBB, PrevBB, LocalVRMap);
400 if (MI->getParent())
401 MI->eraseFromParent();
402 }
403
404 // Now copy the non-PHI instructions.
405 while (I != TailBB->end()) {
406 // Replace def of virtual registers with new registers, and update
407 // uses with PHI source register or the new registers.
408 MachineInstr *MI = &*I++;
409 DuplicateInstruction(MI, TailBB, PrevBB, MF, LocalVRMap);
410 MI->eraseFromParent();
411 }
412 } else {
413 // No PHIs to worry about, just splice the instructions over.
414 PrevBB->splice(PrevBB->end(), TailBB, TailBB->begin(), TailBB->end());
415 }
416 PrevBB->removeSuccessor(PrevBB->succ_begin());
417 assert(PrevBB->succ_empty());
418 PrevBB->transferSuccessors(TailBB);
419 NewTailBB = PrevBB;
351420 Changed = true;
421 }
422
423 if (!PreRegAlloc)
424 return Changed;
425
426 // TailBB's immediate successors are now successors of those predecessors
427 // which duplicated TailBB. Add the predecessors as sources to the PHI
428 // instructions.
429 UpdateSuccessorsPHIs(TailBB, NewTailBB, Succs);
430
431 if (!SSAUpdateVRs.empty()) {
432 // Update SSA form.
433 MachineSSAUpdater SSAUpdate(MF);
434 for (unsigned i = 0, e = SSAUpdateVRs.size(); i != e; ++i) {
435 unsigned VReg = SSAUpdateVRs[i];
436 SSAUpdate.Initialize(VReg);
437
438 // If the original definition is still around, add it as an available
439 // value.
440 MachineInstr *DefMI = MRI->getVRegDef(VReg);
441 MachineBasicBlock *DefBB = 0;
442 if (DefMI) {
443 DefBB = DefMI->getParent();
444 SSAUpdate.AddAvailableValue(DefBB, VReg);
445 }
446
447 // Add the new vregs as available values.
448 DenseMap::iterator LI =
449 SSAUpdateVals.find(VReg);
450 for (unsigned j = 0, ee = LI->second.size(); j != ee; ++j) {
451 unsigned NewReg = LI->second[j];
452 MachineInstr *DefMI = MRI->getVRegDef(NewReg);
453 SSAUpdate.AddAvailableValue(DefMI->getParent(), NewReg);
454 }
455
456 // Rewrite uses that are outside of the original def's block.
457 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
458 while (UI != MRI->use_end()) {
459 MachineOperand &UseMO = UI.getOperand();
460 MachineInstr *UseMI = &*UI;
461 ++UI;
462 if (UseMI->getParent() != DefBB)
463 SSAUpdate.RewriteUse(UseMO);
464 }
465 }
466
467 SSAUpdateVRs.clear();
468 SSAUpdateVals.clear();
352469 }
353470
354471 return Changed;