llvm.org GIT mirror llvm / 79944ce
Merging r201841: ------------------------------------------------------------------------ r201841 | Kevin.Qin | 2014-02-21 02:45:48 -0500 (Fri, 21 Feb 2014) | 2 lines [AArch64] Add register constraints to avoid generating STLXR and STXR with unpredictable behavior. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205903 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
2 changed file(s) with 82 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
25862586 pat, itin> {
25872587 let mayStore = 1;
25882588 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
2589 let Constraints = "@earlyclobber $Rs";
25892590 }
25902591
25912592 multiclass A64I_SRex opcode, string prefix> {
0 ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-REG %s
12
23 @var8 = global i8 0
34 @var16 = global i16 0
1617 ; w0 below is a reasonable guess but could change: it certainly comes into the
1718 ; function there.
1819 ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
20 ; CHECK-REG: add w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
21 ; CHECK-REG-NOT: stlxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
1922 ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
2023 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
2124 ; CHECK-NOT: dmb
3639 ; w0 below is a reasonable guess but could change: it certainly comes into the
3740 ; function there.
3841 ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
42 ; CHECK-REG: add w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
43 ; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
3944 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
4045 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
4146 ; CHECK-NOT: dmb
5661 ; w0 below is a reasonable guess but could change: it certainly comes into the
5762 ; function there.
5863 ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
64 ; CHECK-REG: add w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
65 ; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
5966 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
6067 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
6168 ; CHECK-NOT: dmb
7683 ; x0 below is a reasonable guess but could change: it certainly comes into the
7784 ; function there.
7885 ; CHECK-NEXT: add [[NEW:x[0-9]+]], x[[OLD]], x0
86 ; CHECK-REG: add x[[NEW:[0-9]+]], x{{[0-9]+}}, x0
87 ; CHECK-REG-NOT: stxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}]
7988 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
8089 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
8190 ; CHECK-NOT: dmb
96105 ; w0 below is a reasonable guess but could change: it certainly comes into the
97106 ; function there.
98107 ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
108 ; CHECK-REG: sub w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
109 ; CHECK-REG-NOT: stxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
99110 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
100111 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
101112 ; CHECK-NOT: dmb
116127 ; w0 below is a reasonable guess but could change: it certainly comes into the
117128 ; function there.
118129 ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
130 ; CHECK-REG: sub w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
131 ; CHECK-REG-NOT: stlxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
119132 ; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
120133 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
121134 ; CHECK-NOT: dmb
136149 ; w0 below is a reasonable guess but could change: it certainly comes into the
137150 ; function there.
138151 ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
152 ; CHECK-REG: sub w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
153 ; CHECK-REG-NOT: stxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
139154 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
140155 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
141156 ; CHECK-NOT: dmb
156171 ; x0 below is a reasonable guess but could change: it certainly comes into the
157172 ; function there.
158173 ; CHECK-NEXT: sub [[NEW:x[0-9]+]], x[[OLD]], x0
174 ; CHECK-REG: sub x[[NEW:[0-9]+]], x{{[0-9]+}}, x0
175 ; CHECK-REG-NOT: stlxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}]
159176 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
160177 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
161178 ; CHECK-NOT: dmb
176193 ; w0 below is a reasonable guess but could change: it certainly comes into the
177194 ; function there.
178195 ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
196 ; CHECK-REG: and w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
197 ; CHECK-REG-NOT: stlxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
179198 ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
180199 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
181200 ; CHECK-NOT: dmb
196215 ; w0 below is a reasonable guess but could change: it certainly comes into the
197216 ; function there.
198217 ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
218 ; CHECK-REG: and w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
219 ; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
199220 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
200221 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
201222 ; CHECK-NOT: dmb
216237 ; w0 below is a reasonable guess but could change: it certainly comes into the
217238 ; function there.
218239 ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
240 ; CHECK-REG: and w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
241 ; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
219242 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
220243 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
221244 ; CHECK-NOT: dmb
236259 ; x0 below is a reasonable guess but could change: it certainly comes into the
237260 ; function there.
238261 ; CHECK-NEXT: and [[NEW:x[0-9]+]], x[[OLD]], x0
262 ; CHECK-REG: and x[[NEW:[0-9]+]], x{{[0-9]+}}, x0
263 ; CHECK-REG-NOT: stxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}]
239264 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
240265 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
241266 ; CHECK-NOT: dmb
256281 ; w0 below is a reasonable guess but could change: it certainly comes into the
257282 ; function there.
258283 ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
284 ; CHECK-REG: orr w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
285 ; CHECK-REG-NOT: stlxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
259286 ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
260287 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
261288 ; CHECK-NOT: dmb
276303 ; w0 below is a reasonable guess but could change: it certainly comes into the
277304 ; function there.
278305 ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
306 ; CHECK-REG: orr w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
307 ; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
279308 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
280309 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
281310 ; CHECK-NOT: dmb
296325 ; w0 below is a reasonable guess but could change: it certainly comes into the
297326 ; function there.
298327 ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
328 ; CHECK-REG: orr w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
329 ; CHECK-REG-NOT: stxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
299330 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
300331 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
301332 ; CHECK-NOT: dmb
316347 ; x0 below is a reasonable guess but could change: it certainly comes into the
317348 ; function there.
318349 ; CHECK-NEXT: orr [[NEW:x[0-9]+]], x[[OLD]], x0
350 ; CHECK-REG: orr x[[NEW:[0-9]+]], x{{[0-9]+}}, x0
351 ; CHECK-REG-NOT: stlxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}]
319352 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
320353 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
321354 ; CHECK-NOT: dmb
336369 ; w0 below is a reasonable guess but could change: it certainly comes into the
337370 ; function there.
338371 ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
372 ; CHECK-REG: eor w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
373 ; CHECK-REG-NOT: stxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
339374 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
340375 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
341376 ; CHECK-NOT: dmb
356391 ; w0 below is a reasonable guess but could change: it certainly comes into the
357392 ; function there.
358393 ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
394 ; CHECK-REG: eor w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
395 ; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
359396 ; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
360397 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
361398 ; CHECK-NOT: dmb
376413 ; w0 below is a reasonable guess but could change: it certainly comes into the
377414 ; function there.
378415 ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
416 ; CHECK-REG: eor w[[NEW:[0-9]+]], w{{[0-9]+}}, w0
417 ; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
379418 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
380419 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
381420 ; CHECK-NOT: dmb
396435 ; x0 below is a reasonable guess but could change: it certainly comes into the
397436 ; function there.
398437 ; CHECK-NEXT: eor [[NEW:x[0-9]+]], x[[OLD]], x0
438 ; CHECK-REG: eor x[[NEW:[0-9]+]], x{{[0-9]+}}, x0
439 ; CHECK-REG-NOT: stxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}]
399440 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
400441 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
401442 ; CHECK-NOT: dmb
415456 ; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
416457 ; w0 below is a reasonable guess but could change: it certainly comes into the
417458 ; function there.
459 ; CHECK-REG-NOT: stxrb w0, w0, [x{{[0-9]+}}]
418460 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
419461 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
420462 ; CHECK-NOT: dmb
434476 ; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
435477 ; w0 below is a reasonable guess but could change: it certainly comes into the
436478 ; function there.
479 ; CHECK-REG-NOT: stlxrh w0, w0, [x{{[0-9]+}}]
437480 ; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
438481 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
439482 ; CHECK-NOT: dmb
453496 ; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
454497 ; w0 below is a reasonable guess but could change: it certainly comes into the
455498 ; function there.
499 ; CHECK-REG-NOT: stlxr w0, w0, [x{{[0-9]+}}]
456500 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
457501 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
458502 ; CHECK-NOT: dmb
472516 ; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
473517 ; x0 below is a reasonable guess but could change: it certainly comes into the
474518 ; function there.
519 ; CHECK-REG-NOT: stxr w0, x0, [x{{[0-9]+}}]
475520 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]]
476521 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
477522 ; CHECK-NOT: dmb
494539 ; function there.
495540 ; CHECK-NEXT: cmp w0, w[[OLD]], sxtb
496541 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
542 ; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, gt
543 ; CHECK-REG-NOT: stxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
497544 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
498545 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
499546 ; CHECK-NOT: dmb
515562 ; function there.
516563 ; CHECK-NEXT: cmp w0, w[[OLD]], sxth
517564 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
565 ; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, gt
566 ; CHECK-REG-NOT: stlxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
518567 ; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
519568 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
520569 ; CHECK-NOT: dmb
536585 ; function there.
537586 ; CHECK-NEXT: cmp w0, w[[OLD]]
538587 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
588 ; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, gt
589 ; CHECK-REG-NOT: stxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
539590 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
540591 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
541592 ; CHECK-NOT: dmb
557608 ; function there.
558609 ; CHECK-NEXT: cmp x0, x[[OLD]]
559610 ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt
611 ; CHECK-REG: csel x[[NEW:[0-9]+]], x{{[0-9]+}}, x0, gt
612 ; CHECK-REG-NOT: stlxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}]
560613 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
561614 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
562615 ; CHECK-NOT: dmb
578631 ; function there.
579632 ; CHECK-NEXT: cmp w0, w[[OLD]], sxtb
580633 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt
634 ; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, lt
635 ; CHECK-REG-NOT: stlxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
581636 ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
582637 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
583638 ; CHECK-NOT: dmb
599654 ; function there.
600655 ; CHECK-NEXT: cmp w0, w[[OLD]], sxth
601656 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt
657 ; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, lt
658 ; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
602659 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
603660 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
604661 ; CHECK-NOT: dmb
620677 ; function there.
621678 ; CHECK-NEXT: cmp w0, w[[OLD]]
622679 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt
680 ; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, lt
681 ; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
623682 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
624683 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
625684 ; CHECK-NOT: dmb
641700 ; function there.
642701 ; CHECK-NEXT: cmp x0, x[[OLD]]
643702 ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lt
703 ; CHECK-REG: csel x[[NEW:[0-9]+]], x{{[0-9]+}}, x0, lt
704 ; CHECK-REG-NOT: stlxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}]
644705 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
645706 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
646707 ; CHECK-NOT: dmb
662723 ; function there.
663724 ; CHECK-NEXT: cmp w0, w[[OLD]], uxtb
664725 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
726 ; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, hi
727 ; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
665728 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
666729 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
667730 ; CHECK-NOT: dmb
683746 ; function there.
684747 ; CHECK-NEXT: cmp w0, w[[OLD]], uxth
685748 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
749 ; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, hi
750 ; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
686751 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
687752 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
688753 ; CHECK-NOT: dmb
704769 ; function there.
705770 ; CHECK-NEXT: cmp w0, w[[OLD]]
706771 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
772 ; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, hi
773 ; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
707774 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
708775 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
709776 ; CHECK-NOT: dmb
725792 ; function there.
726793 ; CHECK-NEXT: cmp x0, x[[OLD]]
727794 ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi
795 ; CHECK-REG: csel x[[NEW:[0-9]+]], x{{[0-9]+}}, x0, hi
796 ; CHECK-REG-NOT: stlxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}]
728797 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
729798 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
730799 ; CHECK-NOT: dmb
746815 ; function there.
747816 ; CHECK-NEXT: cmp w0, w[[OLD]], uxtb
748817 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo
818 ; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, lo
819 ; CHECK-REG-NOT: stlxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
749820 ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
750821 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
751822 ; CHECK-NOT: dmb
767838 ; function there.
768839 ; CHECK-NEXT: cmp w0, w[[OLD]], uxth
769840 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo
841 ; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, lo
842 ; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
770843 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
771844 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
772845 ; CHECK-NOT: dmb
788861 ; function there.
789862 ; CHECK-NEXT: cmp w0, w[[OLD]]
790863 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo
864 ; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, lo
865 ; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}]
791866 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
792867 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
793868 ; CHECK-NOT: dmb
809884 ; function there.
810885 ; CHECK-NEXT: cmp x0, x[[OLD]]
811886 ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lo
887 ; CHECK-REG: csel x[[NEW:[0-9]+]], x{{[0-9]+}}, x0, lo
888 ; CHECK-REG-NOT: stlxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}]
812889 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
813890 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
814891 ; CHECK-NOT: dmb
831908 ; CHECK-NEXT: cmp w[[OLD]], w0
832909 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
833910 ; As above, w1 is a reasonable guess.
911 ; CHECK-REG-NOT: stxrb w1, w1, [x{{[0-9]+}}]
834912 ; CHECK: stxrb [[STATUS:w[0-9]+]], w1, [x[[ADDR]]]
835913 ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
836914 ; CHECK-NOT: dmb
853931 ; CHECK-NEXT: cmp w[[OLD]], w0
854932 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
855933 ; As above, w1 is a reasonable guess.
934 ; CHECK-REG-NOT: stlxrh w1, w1, [x{{[0-9]+}}]
856935 ; CHECK: stlxrh [[STATUS:w[0-9]+]], w1, [x[[ADDR]]]
857936 ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
858937 ; CHECK-NOT: dmb
875954 ; CHECK-NEXT: cmp w[[OLD]], w0
876955 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
877956 ; As above, w1 is a reasonable guess.
957 ; CHECK-REG-NOT: stlxr w1, w1, [x{{[0-9]+}}]
878958 ; CHECK: stlxr [[STATUS:w[0-9]+]], w1, [x[[ADDR]]]
879959 ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
880960 ; CHECK-NOT: dmb
897977 ; CHECK-NEXT: cmp x[[OLD]], x0
898978 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
899979 ; As above, w1 is a reasonable guess.
980 ; CHECK-REG-NOT: stxr w1, x1, [x{{[0-9]+}}]
900981 ; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]]
901982 ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
902983 ; CHECK-NOT: dmb