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Merging r266438: ------------------------------------------------------------------------ r266438 | niravd | 2016-04-15 08:01:38 -0700 (Fri, 15 Apr 2016) | 15 lines Fix typing on generated LXV2DX/STXV2DX instructions [PPC] Previously when casting generic loads to LXV2DX/ST instructions we would leave the original load return type in place allowing for an assertion failure when we merge two equivalent LXV2DX nodes with different types. This fixes PR27350. Reviewers: nemanjai Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19133 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@271217 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
2 changed file(s) with 49 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
1010810108 MVT VecTy = N->getValueType(0).getSimpleVT();
1010910109 SDValue LoadOps[] = { Chain, Base };
1011010110 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
10111 DAG.getVTList(VecTy, MVT::Other),
10112 LoadOps, VecTy, MMO);
10111 DAG.getVTList(MVT::v2f64, MVT::Other),
10112 LoadOps, MVT::v2f64, MMO);
10113
1011310114 DCI.AddToWorklist(Load.getNode());
1011410115 Chain = Load.getValue(1);
10115 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10116 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
10116 SDValue Swap = DAG.getNode(
10117 PPCISD::XXSWAPD, dl, DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Load);
1011710118 DCI.AddToWorklist(Swap.getNode());
10119
10120 // Add a bitcast if the resulting load type doesn't match v2f64.
10121 if (VecTy != MVT::v2f64) {
10122 SDValue N = DAG.getNode(ISD::BITCAST, dl, VecTy, Swap);
10123 DCI.AddToWorklist(N.getNode());
10124 // Package {bitcast value, swap's chain} to match Load's shape.
10125 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other),
10126 N, Swap.getValue(1));
10127 }
10128
1011810129 return Swap;
1011910130 }
1012010131
1015810169
1015910170 SDValue Src = N->getOperand(SrcOpnd);
1016010171 MVT VecTy = Src.getValueType().getSimpleVT();
10172
10173 // All stores are done as v2f64 and possible bit cast.
10174 if (VecTy != MVT::v2f64) {
10175 Src = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Src);
10176 DCI.AddToWorklist(Src.getNode());
10177 }
10178
1016110179 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10162 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
10180 DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Src);
1016310181 DCI.AddToWorklist(Swap.getNode());
1016410182 Chain = Swap.getValue(1);
1016510183 SDValue StoreOps[] = { Chain, Swap, Base };
0 ; RUN: llc -mcpu=ppc64le -mtriple=powerpc64le-unknown-linux-gnu < %s
1
2 ; Function Attrs: argmemonly nounwind
3 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #0
4
5 ; Function Attrs: nounwind
6 define internal fastcc void @foo() unnamed_addr #1 align 2 {
7 entry:
8 call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* null, i64 16, i32 8, i1 false)
9 %0 = load <2 x i64>, <2 x i64>* null, align 8
10 %1 = extractelement <2 x i64> %0, i32 1
11 %.fca.1.insert159.i = insertvalue [2 x i64] undef, i64 %1, 1
12 tail call fastcc void @bar([2 x i64] undef, [2 x i64] %.fca.1.insert159.i) #2
13 unreachable
14 }
15
16 ; Function Attrs: nounwind
17 declare fastcc void @bar([2 x i64], [2 x i64]) unnamed_addr #1 align 2
18
19 attributes #0 = { argmemonly nounwind }
20 attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
21 attributes #2 = { nounwind }
22
23 !llvm.ident = !{!0}
24
25 !0 = !{!"clang version 3.9.0 (trunk) (llvm/trunk 266222)"}