llvm.org GIT mirror llvm / 79402ee
Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254843 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 4 years ago
21 changed file(s) with 101 addition(s) and 99 deletion(s). Raw diff Collapse all Expand all
368368 /// AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive
369369 /// registers. If this is not possible, return zero. Otherwise, return the first
370370 /// register of the block that were allocated, marking the entire block as allocated.
371 unsigned AllocateRegBlock(ArrayRef<uint16_t> Regs, unsigned RegsRequired) {
371 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) {
372372 if (RegsRequired > Regs.size())
373373 return 0;
374374
1414 #ifndef LLVM_MC_MCINSTRDESC_H
1515 #define LLVM_MC_MCINSTRDESC_H
1616
17 #include "llvm/MC/MCRegisterInfo.h"
1718 #include "llvm/Support/DataTypes.h"
1819 #include
1920
2021 namespace llvm {
2122 class MCInst;
22 class MCRegisterInfo;
2323 class MCSubtargetInfo;
2424 class FeatureBitset;
2525
136136 /// directly to describe itself.
137137 class MCInstrDesc {
138138 public:
139 unsigned short Opcode; // The opcode number
140 unsigned short NumOperands; // Num of args (may be more if variable_ops)
141 unsigned char NumDefs; // Num of args that are definitions
142 unsigned char Size; // Number of bytes in encoding.
143 unsigned short SchedClass; // enum identifying instr sched class
144 uint64_t Flags; // Flags identifying machine instr class
145 uint64_t TSFlags; // Target Specific Flag values
146 const uint16_t *ImplicitUses; // Registers implicitly read by this instr
147 const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
148 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
139 unsigned short Opcode; // The opcode number
140 unsigned short NumOperands; // Num of args (may be more if variable_ops)
141 unsigned char NumDefs; // Num of args that are definitions
142 unsigned char Size; // Number of bytes in encoding.
143 unsigned short SchedClass; // enum identifying instr sched class
144 uint64_t Flags; // Flags identifying machine instr class
145 uint64_t TSFlags; // Target Specific Flag values
146 const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr
147 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
148 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
149149 // Subtarget feature that this is deprecated on, if any
150150 // -1 implies this is not deprecated by any single feature. It may still be
151151 // deprecated due to a "complex" reason, below.
471471 /// marked as implicitly reading the 'CL' register, which it always does.
472472 ///
473473 /// This method returns null if the instruction has no implicit uses.
474 const uint16_t *getImplicitUses() const { return ImplicitUses; }
474 const MCPhysReg *getImplicitUses() const { return ImplicitUses; }
475475
476476 /// \brief Return the number of implicit uses this instruction has.
477477 unsigned getNumImplicitUses() const {
493493 /// EAX/EDX/EFLAGS registers.
494494 ///
495495 /// This method returns null if the instruction has no implicit defs.
496 const uint16_t *getImplicitDefs() const { return ImplicitDefs; }
496 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; }
497497
498498 /// \brief Return the number of implicit defs this instruct has.
499499 unsigned getNumImplicitDefs() const {
508508 /// \brief Return true if this instruction implicitly
509509 /// uses the specified physical register.
510510 bool hasImplicitUseOfPhysReg(unsigned Reg) const {
511 if (const uint16_t *ImpUses = ImplicitUses)
511 if (const MCPhysReg *ImpUses = ImplicitUses)
512512 for (; *ImpUses; ++ImpUses)
513513 if (*ImpUses == Reg)
514514 return true;
744744 // Gather all the expected implicit operands.
745745 SmallVector ImplicitOperands;
746746 if (MCID.ImplicitDefs)
747 for (const uint16_t *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
747 for (const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
748748 ImplicitOperands.push_back(
749749 MachineOperand::CreateReg(*ImpDefs, true, true));
750750 if (MCID.ImplicitUses)
751 for (const uint16_t *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
751 for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
752752 ImplicitOperands.push_back(
753753 MachineOperand::CreateReg(*ImpUses, false, true));
754754
630630
631631 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
632632 if (MCID->ImplicitDefs)
633 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
633 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
634 ++ImpDefs)
634635 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
635636 if (MCID->ImplicitUses)
636 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
637 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
638 ++ImpUses)
637639 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
638640 }
639641
439439 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
440440 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
441441 NumRes = MCID.getNumDefs();
442 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
442 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
443443 if (Reg == *ImpDef)
444444 break;
445445 ++NumRes;
518518 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
519519 if (!MCID.ImplicitDefs)
520520 continue;
521 for (const uint16_t *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) {
521 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) {
522522 CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
523523 }
524524 }
12051205 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
12061206 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
12071207 NumRes = MCID.getNumDefs();
1208 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
1208 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
12091209 if (Reg == *ImpDef)
12101210 break;
12111211 ++NumRes;
13341334 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
13351335 if (!MCID.ImplicitDefs)
13361336 continue;
1337 for (const uint16_t *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)
1337 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)
13381338 CheckForLiveRegDef(SU, *Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
13391339 }
13401340
27192719 ScheduleDAGRRList *scheduleDAG,
27202720 const TargetInstrInfo *TII,
27212721 const TargetRegisterInfo *TRI) {
2722 const uint16_t *ImpDefs
2722 const MCPhysReg *ImpDefs
27232723 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
27242724 const uint32_t *RegMask = getNodeRegMask(SU->getNode());
27252725 if(!ImpDefs && !RegMask)
27382738 return true;
27392739
27402740 if (ImpDefs)
2741 for (const uint16_t *ImpDef = ImpDefs; *ImpDef; ++ImpDef)
2741 for (const MCPhysReg *ImpDef = ImpDefs; *ImpDef; ++ImpDef)
27422742 // Return true if SU clobbers this physical register use and the
27432743 // definition of the register reaches from DepSU. IsReachable queries
27442744 // a topological forward sort of the DAG (following the successors).
27572757 const TargetRegisterInfo *TRI) {
27582758 SDNode *N = SuccSU->getNode();
27592759 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2760 const uint16_t *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
2760 const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
27612761 assert(ImpDefs && "Caller should check hasPhysRegDefs");
27622762 for (const SDNode *SUNode = SU->getNode(); SUNode;
27632763 SUNode = SUNode->getGluedNode()) {
27642764 if (!SUNode->isMachineOpcode())
27652765 continue;
2766 const uint16_t *SUImpDefs =
2766 const MCPhysReg *SUImpDefs =
27672767 TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
27682768 const uint32_t *SURegMask = getNodeRegMask(SUNode);
27692769 if (!SUImpDefs && !SURegMask)
5252
5353 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
5454 const MCRegisterInfo *MRI) const {
55 if (const uint16_t *ImpDefs = ImplicitDefs)
55 if (const MCPhysReg *ImpDefs = ImplicitDefs)
5656 for (; *ImpDefs; ++ImpDefs)
5757 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
5858 return true;
47524752 }
47534753
47544754 // Consider implicit defs to be clobbers. Think of cpuid and push.
4755 ArrayRef ImpDefs(Desc.getImplicitDefs(),
4756 Desc.getNumImplicitDefs());
4755 ArrayRef ImpDefs(Desc.getImplicitDefs(),
4756 Desc.getNumImplicitDefs());
47574757 ClobberRegs.insert(ClobberRegs.end(), ImpDefs.begin(), ImpDefs.end());
47584758 }
47594759
2424 namespace {
2525 using namespace llvm;
2626
27 static const uint16_t XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
28 AArch64::X3, AArch64::X4, AArch64::X5,
29 AArch64::X6, AArch64::X7};
30 static const uint16_t HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
31 AArch64::H3, AArch64::H4, AArch64::H5,
32 AArch64::H6, AArch64::H7};
33 static const uint16_t SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
34 AArch64::S3, AArch64::S4, AArch64::S5,
35 AArch64::S6, AArch64::S7};
36 static const uint16_t DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
37 AArch64::D3, AArch64::D4, AArch64::D5,
38 AArch64::D6, AArch64::D7};
39 static const uint16_t QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
40 AArch64::Q3, AArch64::Q4, AArch64::Q5,
41 AArch64::Q6, AArch64::Q7};
27 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
28 AArch64::X3, AArch64::X4, AArch64::X5,
29 AArch64::X6, AArch64::X7};
30 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
31 AArch64::H3, AArch64::H4, AArch64::H5,
32 AArch64::H6, AArch64::H7};
33 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
34 AArch64::S3, AArch64::S4, AArch64::S5,
35 AArch64::S6, AArch64::S7};
36 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
37 AArch64::D3, AArch64::D4, AArch64::D5,
38 AArch64::D6, AArch64::D7};
39 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
40 AArch64::Q3, AArch64::Q4, AArch64::Q5,
41 AArch64::Q6, AArch64::Q7};
4242
4343 static bool finishStackBlock(SmallVectorImpl &PendingMembers,
4444 MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
8585 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
8686 // Try to allocate a contiguous block of registers, each of the correct
8787 // size to hold one member.
88 ArrayRef<uint16_t> RegList;
88 ArrayRef<MCPhysReg> RegList;
8989 if (LocVT.SimpleTy == MVT::i64)
9090 RegList = XRegList;
9191 else if (LocVT.SimpleTy == MVT::f16)
159159 State);
160160 }
161161
162 static const uint16_t RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
163
164 static const uint16_t SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
165 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
166 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
167 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
168 static const uint16_t DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
169 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
170 static const uint16_t QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
162 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
163
164 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
165 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
166 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
167 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
168 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
169 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
170 static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 };
171171
172172
173173 // Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA
202202 unsigned StackAlign = DL.getStackAlignment();
203203 unsigned Align = std::min(PendingMembers[0].getExtraInfo(), StackAlign);
204204
205 ArrayRef<uint16_t> RegList;
205 ArrayRef<MCPhysReg> RegList;
206206 switch (LocVT.SimpleTy) {
207207 case MVT::i32: {
208208 RegList = RRegList;
30353035 }
30363036
30373037
3038 static const uint16_t GPRArgRegs[] = {
3038 static const MCPhysReg GPRArgRegs[] = {
30393039 ARM::R0, ARM::R1, ARM::R2, ARM::R3
30403040 };
30413041
217217 }
218218
219219 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
220 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
220 for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
221221 if (*Regs == ARM::CPSR)
222222 return true;
223223 return false;
470470 }
471471
472472 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
473 ArrayRef<uint16_t> Table) {
473 ArrayRef<MCPhysReg> Table) {
474474 if (RegNo < Table.size()) {
475475 Inst.addOperand(MCOperand::createReg(Table[RegNo]));
476476 return MCDisassembler::Success;
488488 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
489489 uint64_t Address,
490490 const void *Decoder) {
491 static const uint16_t IntRegDecoderTable[] = {
491 static const MCPhysReg IntRegDecoderTable[] = {
492492 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
493493 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
494494 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
497497 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
498498 Hexagon::R30, Hexagon::R31};
499499
500 return (DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable));
500 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
501501 }
502502
503503 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
504504 uint64_t /*Address*/,
505505 const void *Decoder) {
506 static const uint16_t VecRegDecoderTable[] = {
506 static const MCPhysReg VecRegDecoderTable[] = {
507507 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
508508 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
509509 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
512512 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
513513 Hexagon::V30, Hexagon::V31};
514514
515 return (DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable));
515 return DecodeRegisterClass(Inst, RegNo, VecRegDecoderTable);
516516 }
517517
518518 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
519519 uint64_t /*Address*/,
520520 const void *Decoder) {
521 static const uint16_t DoubleRegDecoderTable[] = {
521 static const MCPhysReg DoubleRegDecoderTable[] = {
522522 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
523523 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
524524 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
525525 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
526526
527 return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable));
527 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
528528 }
529529
530530 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
531531 uint64_t /*Address*/,
532532 const void *Decoder) {
533 static const uint16_t VecDblRegDecoderTable[] = {
533 static const MCPhysReg VecDblRegDecoderTable[] = {
534534 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
535535 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7,
536536 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11,
542542 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
543543 uint64_t /*Address*/,
544544 const void *Decoder) {
545 static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
546 Hexagon::P2, Hexagon::P3};
547
548 return (DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable));
545 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
546 Hexagon::P2, Hexagon::P3};
547
548 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
549549 }
550550
551551 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
552552 uint64_t /*Address*/,
553553 const void *Decoder) {
554 static const uint16_t VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
555 Hexagon::Q2, Hexagon::Q3};
556
557 return (DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable));
554 static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
555 Hexagon::Q2, Hexagon::Q3};
556
557 return DecodeRegisterClass(Inst, RegNo, VecPredRegDecoderTable);
558558 }
559559
560560 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
561561 uint64_t /*Address*/,
562562 const void *Decoder) {
563 static const uint16_t CtrlRegDecoderTable[] = {
563 static const MCPhysReg CtrlRegDecoderTable[] = {
564564 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
565565 Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7,
566566 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,
581581 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
582582 uint64_t /*Address*/,
583583 const void *Decoder) {
584 static const uint16_t CtrlReg64DecoderTable[] = {
584 static const MCPhysReg CtrlReg64DecoderTable[] = {
585585 Hexagon::C1_0, Hexagon::NoRegister,
586586 Hexagon::C3_2, Hexagon::NoRegister,
587587 Hexagon::C7_6, Hexagon::NoRegister,
119119 // First, get the implicit defs and uses for this instruction.
120120 unsigned Opc = MI->getOpcode();
121121 const MCInstrDesc &D = HII->get(Opc);
122 if (const uint16_t *R = D.ImplicitDefs)
122 if (const MCPhysReg *R = D.ImplicitDefs)
123123 while (*R)
124124 expandReg(*R++, Defs);
125 if (const uint16_t *R = D.ImplicitUses)
125 if (const MCPhysReg *R = D.ImplicitUses)
126126 while (*R)
127127 expandReg(*R++, Uses);
128128
315315 MVT LocVT, CCValAssign::LocInfo LocInfo,
316316 ISD::ArgFlagsTy ArgFlags, CCState &State) {
317317
318 static const uint16_t VecLstS[] = { Hexagon::V0, Hexagon::V1,
319 Hexagon::V2, Hexagon::V3,
320 Hexagon::V4, Hexagon::V5,
321 Hexagon::V6, Hexagon::V7,
322 Hexagon::V8, Hexagon::V9,
323 Hexagon::V10, Hexagon::V11,
324 Hexagon::V12, Hexagon::V13,
325 Hexagon::V14, Hexagon::V15};
326 static const uint16_t VecLstD[] = { Hexagon::W0, Hexagon::W1,
327 Hexagon::W2, Hexagon::W3,
328 Hexagon::W4, Hexagon::W5,
329 Hexagon::W6, Hexagon::W7};
318 static const MCPhysReg VecLstS[] = { Hexagon::V0, Hexagon::V1,
319 Hexagon::V2, Hexagon::V3,
320 Hexagon::V4, Hexagon::V5,
321 Hexagon::V6, Hexagon::V7,
322 Hexagon::V8, Hexagon::V9,
323 Hexagon::V10, Hexagon::V11,
324 Hexagon::V12, Hexagon::V13,
325 Hexagon::V14, Hexagon::V15};
326 static const MCPhysReg VecLstD[] = { Hexagon::W0, Hexagon::W1,
327 Hexagon::W2, Hexagon::W3,
328 Hexagon::W4, Hexagon::W5,
329 Hexagon::W6, Hexagon::W7};
330330 auto &MF = State.getMachineFunction();
331331 auto &HST = MF.getSubtarget();
332332 bool UseHVX = HST.useHVXOps();
8484 }
8585
8686 // Get implicit register definitions.
87 const uint16_t* ImpDefs = MCID.getImplicitDefs();
87 const MCPhysReg *ImpDefs = MCID.getImplicitDefs();
8888 for (unsigned i = 0; i < MCID.getNumImplicitDefs(); ++i) {
8989 unsigned R = ImpDefs[i];
9090
333333 // The only relocs left should be GP relative:
334334 default:
335335 if (MCID.mayStore() || MCID.mayLoad()) {
336 for (const uint16_t *ImpUses = MCID.getImplicitUses(); *ImpUses;
336 for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
337337 ++ImpUses) {
338338 if (*ImpUses == Hexagon::GP) {
339339 switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
2929
3030 /// VRRegNo - Map from a numbered VR register to its enum value.
3131 ///
32 static const uint16_t VRRegNo[] = {
32 static const MCPhysReg VRRegNo[] = {
3333 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
3434 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
3535 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
17471747 MI->setDesc(NewDesc);
17481748
17491749 if (NewDesc.ImplicitDefs)
1750 for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs();
1750 for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
17511751 *ImpDefs; ++ImpDefs)
17521752 if (!MI->definesRegister(*ImpDefs))
17531753 MI->addOperand(*MI->getParent()->getParent(),
17541754 MachineOperand::CreateReg(*ImpDefs, true, true));
17551755 if (NewDesc.ImplicitUses)
1756 for (const uint16_t *ImpUses = NewDesc.getImplicitUses();
1756 for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
17571757 *ImpUses; ++ImpUses)
17581758 if (!MI->readsRegister(*ImpUses))
17591759 MI->addOperand(*MI->getParent()->getParent(),
638638 /// \brief Get the compact unwind number for a given register. The number
639639 /// corresponds to the enum lists in compact_unwind_encoding.h.
640640 int getCompactUnwindRegNum(unsigned Reg) const {
641 static const uint16_t CU32BitRegs[7] = {
641 static const MCPhysReg CU32BitRegs[7] = {
642642 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
643643 };
644 static const uint16_t CU64BitRegs[] = {
644 static const MCPhysReg CU64BitRegs[] = {
645645 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
646646 };
647 const uint16_t *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
647 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
648648 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
649649 if (*CURegs == Reg)
650650 return Idx;
7373
7474 static void PrintDefList(const std::vector &Uses,
7575 unsigned Num, raw_ostream &OS) {
76 OS << "static const uint16_t ImplicitList" << Num << "[] = { ";
76 OS << "static const MCPhysReg ImplicitList" << Num << "[] = { ";
7777 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
7878 OS << getQualifiedName(Uses[i]) << ", ";
7979 OS << "0 };\n";