llvm.org GIT mirror llvm / 793ce99
[SystemZ] Automatically detect zEC12 and z196 hosts As on other hosts, the CPU identification instruction is priveleged, so we need to look through /proc/cpuinfo. I copied the PowerPC way of handling "generic". Several tests were implicitly assuming z10 and so failed on z196. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193742 91177308-0d34-0410-b5e6-96231b3b80d8 Richard Sandiford 6 years ago
23 changed file(s) with 127 addition(s) and 49 deletion(s). Raw diff Collapse all Expand all
534534
535535 return "generic";
536536 }
537 #elif defined(__linux__) && defined(__s390x__)
538 std::string sys::getHostCPUName() {
539 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
540 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
541 // memory buffer because the 'file' has 0 size (it can be read from only
542 // as a stream).
543
544 std::string Err;
545 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
546 if (!DS) {
547 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
548 return "generic";
549 }
550
551 // The "processor 0:" line comes after a fair amount of other information,
552 // including a cache breakdown, but this should be plenty.
553 char buffer[2048];
554 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
555 delete DS;
556
557 StringRef Str(buffer, CPUInfoSize);
558 SmallVector Lines;
559 Str.split(Lines, "\n");
560 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
561 if (Lines[I].startswith("processor ")) {
562 size_t Pos = Lines[I].find("machine = ");
563 if (Pos != StringRef::npos) {
564 Pos += sizeof("machine = ") - 1;
565 unsigned int Id;
566 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
567 if (Id >= 2827)
568 return "zEC12";
569 if (Id >= 2817)
570 return "z196";
571 }
572 }
573 break;
574 }
575 }
576
577 return "generic";
578 }
537579 #else
538580 std::string sys::getHostCPUName() {
539581 return "generic";
3535 "Assume that the floating-point extension facility is installed"
3636 >;
3737
38 def : Processor<"z10", NoItineraries, []>;
39 def : Processor<"z196", NoItineraries,
38 def : Processor<"generic", NoItineraries, []>;
39 def : Processor<"z10", NoItineraries, []>;
40 def : Processor<"z196", NoItineraries,
4041 [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
4142 FeatureFPExtension]>;
4243 def : Processor<"zEC12", NoItineraries,
88
99 #include "SystemZSubtarget.h"
1010 #include "llvm/IR/GlobalValue.h"
11 #include "llvm/Support/Host.h"
1112 #include "MCTargetDesc/SystemZMCTargetDesc.h"
1213
1314 #define GET_SUBTARGETINFO_TARGET_DESC
2425 TargetTriple(TT) {
2526 std::string CPUName = CPU;
2627 if (CPUName.empty())
27 CPUName = "z10";
28 CPUName = "generic";
29 #if defined(__linux__) && defined(__s390x__)
30 if (CPUName == "generic")
31 CPUName = sys::getHostCPUName();
32 #endif
2833
2934 // Parse features string.
3035 ParseSubtargetFeatures(CPUName, FS);
None ; Test 32-bit atomic minimum and maximum.
0 ; Test 32-bit atomic minimum and maximum. Here we match the z10 versions,
1 ; which can't use LOCR.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 ; Check signed minium.
56 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
None ; Test 64-bit atomic minimum and maximum.
0 ; Test 64-bit atomic minimum and maximum. Here we match the z10 versions,
1 ; which can't use LOCGR.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 ; Check signed minium.
56 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
None ; Test 8-bit conditional stores that are presented as selects.
0 ; Test 8-bit conditional stores that are presented as selects. The volatile
1 ; tests require z10, which use a branch instead of a LOCR.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 declare void @foo(i8 *)
56
None ; Test 16-bit conditional stores that are presented as selects.
0 ; Test 16-bit conditional stores that are presented as selects. The volatile
1 ; tests require z10, which use a branch instead of a LOCR.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 declare void @foo(i16 *)
56
None ; Test 32-bit floating-point comparison.
0 ; Test 32-bit floating-point comparison. The tests assume a z10 implementation
1 ; of select, using conditional branches rather than LOCGR.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 declare float @foo()
56
None ; Test 64-bit floating-point comparison.
0 ; Test 64-bit floating-point comparison. The tests assume a z10 implementation
1 ; of select, using conditional branches rather than LOCGR.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 declare double @foo()
56
None ; Test 128-bit floating-point comparison.
0 ; Test 128-bit floating-point comparison. The tests assume a z10 implementation
1 ; of select, using conditional branches rather than LOCGR.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 ; There is no memory form of 128-bit comparison.
56 define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) {
None ; Test moves between FPRs and GPRs.
0 ; Test moves between FPRs and GPRs. The 32-bit cases test the z10
1 ; implementation, which has no high-word support.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 declare i64 @foo()
56 declare double @bar()
0 ; Test the handling of base + 12-bit displacement addresses for large frames,
1 ; in cases where no 20-bit form exists.
2 ;
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s
1 ; in cases where no 20-bit form exists. The tests here assume z10 register
2 ; pressure, without the high words being available.
3 ;
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \
5 ; RUN: FileCheck -check-prefix=CHECK-NOFP %s
6 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -disable-fp-elim | \
7 ; RUN: FileCheck -check-prefix=CHECK-FP %s
58
69 ; This file tests what happens when a displacement is converted from
710 ; being relative to the start of a frame object to being relative to
0 ; Test the handling of base + displacement addresses for large frames,
11 ; in cases where both 12-bit and 20-bit displacements are allowed.
2 ;
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s
5
2 ; The tests here assume z10 register pressure, without the high words
3 ; being available.
4 ;
5 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \
6 ; RUN: FileCheck -check-prefix=CHECK-NOFP %s
7 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -disable-fp-elim | \
8 ; RUN: FileCheck -check-prefix=CHECK-FP %s
9 ;
610 ; This file tests what happens when a displacement is converted from
711 ; being relative to the start of a frame object to being relative to
812 ; the frame itself. In some cases the test is only possible if two
0 ; Test the handling of base + index + 12-bit displacement addresses for
1 ; large frames, in cases where no 20-bit form exists.
2 ;
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s
1 ; large frames, in cases where no 20-bit form exists. The tests here
2 ; assume z10 register pressure, without the high words being available.
3 ;
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \
5 ; RUN: FileCheck -check-prefix=CHECK-NOFP %s
6 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -disable-fp-elim | \
7 ; RUN: FileCheck -check-prefix=CHECK-FP %s
58
69 declare void @foo(float *%ptr1, float *%ptr2)
710
0 ; Test the handling of base + index + displacement addresses for large frames,
11 ; in cases where both 12-bit and 20-bit displacements are allowed.
2 ;
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s
4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s
2 ; The tests here assume z10 register pressure, without the high words
3 ; being available.
4 ;
5 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | \
6 ; RUN: FileCheck -check-prefix=CHECK-NOFP %s
7 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 -disable-fp-elim | \
8 ; RUN: FileCheck -check-prefix=CHECK-FP %s
59
610 ; This file tests what happens when a displacement is converted from
711 ; being relative to the start of a frame object to being relative to
None ; Test spilling of GPRs.
0 ; Test spilling of GPRs. The tests here assume z10 register pressure,
1 ; without the high words being available.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 ; We need to allocate a 4-byte spill slot, rounded to 8 bytes. The frame
56 ; size should be exactly 160 + 8 = 168.
None ; Test 32-bit additions of constants to memory.
0 ; Test 32-bit additions of constants to memory. The tests here
1 ; assume z10 register pressure, without the high words being available.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 ; Check additions of 1.
56 define void @f1(i32 *%ptr) {
None ; Test zero extensions from a byte to an i32.
0 ; Test zero extensions from a byte to an i32. The tests here
1 ; assume z10 register pressure, without the high words being available.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 ; Test register extension, starting with an i32.
56 define i32 @f1(i32 %a) {
None ; Test zero extensions from a halfword to an i32.
0 ; Test zero extensions from a halfword to an i32. The tests here
1 ; assume z10 register pressure, without the high words being available.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 ; Test register extension, starting with an i32.
56 define i32 @f1(i32 %a) {
0 ; Test sequences that can use RISBG with a zeroed first operand.
1 ; The tests here assume that RISBLG isn't available.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 ; Test an extraction of bit 0 from a right-shifted value.
56 define i32 @f1(i32 %foo) {
None ; Test SETCC for every integer condition.
0 ; Test SETCC for every integer condition. The tests here assume that
1 ; RISBLG isn't available.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 ; Test CC in { 0 }, with 3 don't care.
56 define i32 @f1(i32 %a, i32 %b) {
None ; Test SETCC for every floating-point condition.
0 ; Test SETCC for every floating-point condition. The tests here assume that
1 ; RISBLG isn't available.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 ; Test CC in { 0 }
56 define i32 @f1(float %a, float %b) {
None ; Test spilling using MVC.
0 ; Test spilling using MVC. The tests here assume z10 register pressure,
1 ; without the high words being available.
12 ;
2 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
34
45 declare void @foo()
56