llvm.org GIT mirror llvm / 78efd69
MachineFunction: Cleanup/simplify MachineFunctionProperties::print() - Always compile print() regardless of LLVM_ENABLE_DUMP. (We usually only gard dump() functions with that). - Only show the set properties to reduce output clutter. - Remove the unused variant that even shows the unset properties. - Fix comments git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279338 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 4 years ago
4 changed file(s) with 23 addition(s) and 41 deletion(s). Raw diff Collapse all Expand all
8383 /// require that a property be set.
8484 class MachineFunctionProperties {
8585 // TODO: Add MachineVerifier checks for AllVRegsAllocated
86 // TODO: Add a way to print the properties and make more useful error messages
8786 // Possible TODO: Allow targets to extend this (perhaps by allowing the
8887 // constructor to specify the size of the bit vector)
8988 // Possible TODO: Allow requiring the negative (e.g. VRegsAllocated could be
154153 return !V.Properties.test(Properties);
155154 }
156155
157 // Print the MachineFunctionProperties in human-readable form. If OnlySet is
158 // true, only print the properties that are set.
159 void print(raw_ostream &ROS, bool OnlySet=false) const;
156 /// Print the MachineFunctionProperties in human-readable form.
157 void print(raw_ostream &OS) const;
160158
161159 private:
162160 BitVector Properties =
5353
5454 void MachineFunctionInitializer::anchor() {}
5555
56 void MachineFunctionProperties::print(raw_ostream &ROS, bool OnlySet) const {
57 // Leave this function even in NDEBUG as an out-of-line anchor.
58 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
59 bool NeedsComma = false;
60 for (BitVector::size_type i = 0; i < Properties.size(); ++i) {
61 bool HasProperty = Properties[i];
62 if (OnlySet && !HasProperty)
56 static const char *getPropertyName(MachineFunctionProperties::Property Prop) {
57 typedef MachineFunctionProperties::Property P;
58 switch(Prop) {
59 case P::AllVRegsAllocated: return "AllVRegsAllocated";
60 case P::IsSSA: return "IsSSA";
61 case P::Legalized: return "Legalized";
62 case P::RegBankSelected: return "RegBankSelected";
63 case P::Selected: return "Selected";
64 case P::TracksLiveness: return "TracksLiveness";
65 }
66 }
67
68 void MachineFunctionProperties::print(raw_ostream &OS) const {
69 const char *Separator = "";
70 for (BitVector::size_type I = 0; I < Properties.size(); ++I) {
71 if (!Properties[I])
6372 continue;
64 if (NeedsComma)
65 ROS << ", ";
66 else
67 NeedsComma = true;
68 switch(static_cast(i)) {
69 case Property::IsSSA:
70 ROS << (HasProperty ? "SSA" : "Post SSA");
71 break;
72 case Property::TracksLiveness:
73 ROS << (HasProperty ? "" : "not ") << "tracking liveness";
74 break;
75 case Property::AllVRegsAllocated:
76 ROS << (HasProperty ? "AllVRegsAllocated" : "HasVRegs");
77 break;
78 case Property::Legalized:
79 ROS << (HasProperty ? "" : "not ") << "legalized";
80 break;
81 case Property::RegBankSelected:
82 ROS << (HasProperty ? "" : "not ") << "RegBank-selected";
83 break;
84 case Property::Selected:
85 ROS << (HasProperty ? "" : "not ") << "selected";
86 break;
87 }
88 }
89 #endif
73 OS << Separator << getPropertyName(static_cast(I));
74 Separator = ", ";
75 }
9076 }
9177
9278 //===----------------------------------------------------------------------===//
417403
418404 void MachineFunction::print(raw_ostream &OS, const SlotIndexes *Indexes) const {
419405 OS << "# Machine code for function " << getName() << ": ";
420 OS << "Properties: <";
421406 getProperties().print(OS);
422 OS << ">\n";
423407
424408 // Print Frame Information
425409 FrameInfo->print(*this, OS);
4848 errs() << "MachineFunctionProperties required by " << getPassName()
4949 << " pass are not met by function " << F.getName() << ".\n"
5050 << "Required properties: ";
51 RequiredProperties.print(errs(), /*OnlySet=*/true);
51 RequiredProperties.print(errs());
5252 errs() << "\nCurrent properties: ";
5353 MFProps.print(errs());
5454 errs() << "\n";
66
77 ; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
88 ;
9 ; CHECK-LABEL: # Machine code for function foo: Properties:
9 ; CHECK-LABEL: # Machine code for function foo:
1010 ; CHECK: SU(2): %W{{[0-9]+}}, %W{{[0-9]+}} = LDPWi
1111 ; CHECK: Successors:
1212 ; CHECK-NOT: ch SU(4)