llvm.org GIT mirror llvm / 78e5c11
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical except it doesn't care if the definitions' virtual registers differ. This is used by machine LICM and other MI passes to perform CSE. - Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical. Since pc relative constantpool entries are always different, this requires it it check if the values can actually the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
7 changed file(s) with 115 addition(s) and 41 deletion(s). Raw diff Collapse all Expand all
2121
2222 #define DEBUG_TYPE "machine-licm"
2323 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
2425 #include "llvm/CodeGen/MachineDominators.h"
2526 #include "llvm/CodeGen/MachineLoopInfo.h"
2627 #include "llvm/CodeGen/MachineMemOperand.h"
4243
4344 namespace {
4445 class MachineLICM : public MachineFunctionPass {
46 MachineConstantPool *MCP;
4547 const TargetMachine *TM;
4648 const TargetInstrInfo *TII;
4749 const TargetRegisterInfo *TRI;
110112 /// be hoistable.
111113 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
112114
115 /// LookForDuplicate - Find an instruction amount PrevMIs that is a
116 /// duplicate of MI. Return this instruction if it's found.
117 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
118 std::vector &PrevMIs);
119
113120 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on
114121 /// the preheader that compute the same value. If it's found, do a RAU on
115122 /// with the definition of the existing instruction rather than hoisting
152159 DEBUG(errs() << "******** Machine LICM ********\n");
153160
154161 Changed = FirstInLoop = false;
162 MCP = MF.getConstantPool();
155163 TM = &MF.getTarget();
156164 TII = TM->getInstrInfo();
157165 TRI = TM->getRegisterInfo();
431439 }
432440 }
433441
434 static const MachineInstr *LookForDuplicate(const MachineInstr *MI,
435 std::vector &PrevMIs,
436 MachineRegisterInfo *RegInfo) {
437 unsigned NumOps = MI->getNumOperands();
442 const MachineInstr*
443 MachineLICM::LookForDuplicate(const MachineInstr *MI,
444 std::vector &PrevMIs) {
438445 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
439446 const MachineInstr *PrevMI = PrevMIs[i];
440 unsigned NumOps2 = PrevMI->getNumOperands();
441 if (NumOps != NumOps2)
442 continue;
443 bool IsSame = true;
444 for (unsigned j = 0; j != NumOps; ++j) {
445 const MachineOperand &MO = MI->getOperand(j);
446 if (MO.isReg() && MO.isDef()) {
447 if (RegInfo->getRegClass(MO.getReg()) !=
448 RegInfo->getRegClass(PrevMI->getOperand(j).getReg())) {
449 IsSame = false;
450 break;
451 }
452 continue;
453 }
454 if (!MO.isIdenticalTo(PrevMI->getOperand(j))) {
455 IsSame = false;
456 break;
457 }
458 }
459 if (IsSame)
447 if (TII->isIdentical(MI, PrevMI, RegInfo))
460448 return PrevMI;
461449 }
462450 return 0;
464452
465453 bool MachineLICM::EliminateCSE(MachineInstr *MI,
466454 DenseMap >::iterator &CI) {
467 if (CI != CSEMap.end()) {
468 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second, RegInfo)) {
469 DEBUG(errs() << "CSEing " << *MI << " with " << *Dup);
470 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
471 const MachineOperand &MO = MI->getOperand(i);
472 if (MO.isReg() && MO.isDef())
473 RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
474 }
475 MI->eraseFromParent();
476 ++NumCSEed;
477 return true;
455 if (CI == CSEMap.end())
456 return false;
457
458 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
459 DEBUG(errs() << "CSEing " << *MI << " with " << *Dup);
460 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
461 const MachineOperand &MO = MI->getOperand(i);
462 if (MO.isReg() && MO.isDef())
463 RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
478464 }
465 MI->eraseFromParent();
466 ++NumCSEed;
467 return true;
479468 }
480469 return false;
481470 }
140140 MO.setReg(DestReg);
141141 MO.setSubReg(SubIdx);
142142 MBB.insert(I, MI);
143 }
144
145 bool
146 TargetInstrInfoImpl::isIdentical(const MachineInstr *MI,
147 const MachineInstr *Other,
148 const MachineRegisterInfo *MRI) const {
149 if (MI->getOpcode() != Other->getOpcode() ||
150 MI->getNumOperands() != Other->getNumOperands())
151 return false;
152
153 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
154 const MachineOperand &MO = MI->getOperand(i);
155 const MachineOperand &OMO = Other->getOperand(i);
156 if (MO.isReg() && MO.isDef()) {
157 assert(OMO.isReg() && OMO.isDef());
158 unsigned Reg = MO.getReg();
159 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
160 if (Reg != OMO.getReg())
161 return false;
162 } else if (MRI->getRegClass(MO.getReg()) !=
163 MRI->getRegClass(OMO.getReg()))
164 return false;
165
166 continue;
167 }
168
169 if (!MO.isIdenticalTo(OMO))
170 return false;
171 }
172
173 return true;
143174 }
144175
145176 unsigned
6161 ARMConstantPoolValue *CPV =
6262 (ARMConstantPoolValue *)Constants[i].Val.MachineCPVal;
6363 if (CPV->CVal == CVal &&
64 CPV->S == S &&
6564 CPV->LabelId == LabelId &&
66 CPV->PCAdjust == PCAdjust)
65 CPV->PCAdjust == PCAdjust &&
66 (CPV->S == S || strcmp(CPV->S, S) == 0) &&
67 (CPV->Modifier == Modifier || strcmp(CPV->Modifier, Modifier) == 0))
6768 return i;
6869 }
6970 }
8384 ID.AddInteger(PCAdjust);
8485 }
8586
87 bool
88 ARMConstantPoolValue::hasSameValue(ARMConstantPoolValue *ACPV) {
89 if (ACPV->Kind == Kind &&
90 ACPV->CVal == CVal &&
91 ACPV->PCAdjust == PCAdjust &&
92 (ACPV->S == S || strcmp(ACPV->S, S) == 0) &&
93 (ACPV->Modifier == Modifier || strcmp(ACPV->Modifier, Modifier) == 0)) {
94 if (ACPV->LabelId == LabelId)
95 return true;
96 // Two PC relative constpool entries containing the same GV address or
97 // external symbols. FIXME: What about blockaddress?
98 if (Kind == ARMCP::CPValue || Kind == ARMCP::CPExtSymbol)
99 return true;
100 }
101 return false;
102 }
103
86104 void ARMConstantPoolValue::dump() const {
87105 errs() << " " << *this;
88106 }
8080
8181 virtual void AddSelectionDAGCSEId(FoldingSetNodeID &ID);
8282
83 /// hasSameValue - Return true if this ARM constpool value
84 /// can share the same constantpool entry as another ARM constpool value.
85 bool hasSameValue(ARMConstantPoolValue *ACPV);
86
8387 void print(raw_ostream *O) const { if (O) print(*O); }
8488 void print(raw_ostream &O) const;
8589 void dump() const;
174174 NewMI->getOperand(0).setSubReg(SubIdx);
175175 }
176176
177 bool Thumb2InstrInfo::isIdentical(const MachineInstr *MI0,
178 const MachineInstr *MI1,
179 const MachineRegisterInfo *MRI) const {
180 unsigned Opcode = MI0->getOpcode();
181 if (Opcode == ARM::t2LDRpci_pic) {
182 const MachineOperand &MO0 = MI0->getOperand(1);
183 const MachineOperand &MO1 = MI1->getOperand(1);
184 if (MO0.getOffset() != MO1.getOffset())
185 return false;
186
187 const MachineFunction *MF = MI0->getParent()->getParent();
188 const MachineConstantPool *MCP = MF->getConstantPool();
189 int CPI0 = MO0.getIndex();
190 int CPI1 = MO1.getIndex();
191 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
192 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
193 ARMConstantPoolValue *ACPV0 =
194 static_cast(MCPE0.Val.MachineCPVal);
195 ARMConstantPoolValue *ACPV1 =
196 static_cast(MCPE1.Val.MachineCPVal);
197 return ACPV0->hasSameValue(ACPV1);
198 }
199
200 return TargetInstrInfoImpl::isIdentical(MI0, MI1, MRI);
201 }
202
177203 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
178204 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
179205 unsigned DestReg, unsigned BaseReg, int NumBytes,
5353 unsigned DestReg, unsigned SubIdx,
5454 const MachineInstr *Orig) const;
5555
56 bool isIdentical(const MachineInstr *MI,
57 const MachineInstr *Other,
58 const MachineRegisterInfo *MRI) const;
59
5660 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
5761 /// such, whenever a client has an instance of instruction info, it should
5862 /// always be able to get register info as well (through this method).
1414
1515 bb.nph: ; preds = %entry
1616 ; CHECK: BB#1
17 ; CHECK: ldr{{.*}} r{{[0-9]+}}, LCPI1_0
18 ; CHECK: ldr{{.*}} r{{[0-9]+}}, LCPI1_1
19 ; CHECK: add r{{[0-9]+}}, pc
20 ; CHECK: add r{{[0-9]+}}, pc
17 ; CHECK: ldr.n r2, LCPI1_0
18 ; CHECK: add r2, pc
19 ; CHECK: ldr r{{[0-9]+}}, [r2]
2120 ; CHECK: LBB1_2
21 ; CHECK: LCPI1_0:
22 ; CHECK-NOT: LCPI1_1:
23 ; CHECK: .section
2224 %.pre = load i32* @GV, align 4 ; [#uses=1]
2325 br label %bb
2426