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Merging r222996: ------------------------------------------------------------------------ r222996 | foad | 2014-12-01 09:42:32 +0000 (Mon, 01 Dec 2014) | 19 lines [PowerPC] Fix unwind info with dynamic stack realignment Summary: PowerPC DWARF unwind info defined CFA as SP + offset even in a function where the stack had been dynamically realigned. This clearly doesn't work because the offset from SP to CFA is not a constant. Fix it by defining CFA as BP instead. This was causing the AddressSanitizer null_deref test to fail 50% of the time, depending on whether SP happened to be 32-byte aligned on entry to a particular function or not. Reviewers: willschm, uweigand, hfinkel Reviewed By: hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6410 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@223744 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 5 years ago
2 changed file(s) with 35 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
504504 MachineModuleInfo &MMI = MF.getMMI();
505505 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
506506 DebugLoc dl;
507 bool needsFrameMoves = MMI.hasDebugInfo() ||
507 bool needsCFI = MMI.hasDebugInfo() ||
508508 MF.getFunction()->needsUnwindTableEntry();
509509 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
510510
725725 .addReg(ScratchReg);
726726 }
727727
728 // Add the "machine moves" for the instructions we generated above, but in
729 // reverse order.
730 if (needsFrameMoves) {
731 // Show update of SP.
732 assert(NegFrameSize);
733 unsigned CFIIndex = MMI.addFrameInst(
734 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
728 // Add Call Frame Information for the instructions we generated above.
729 if (needsCFI) {
730 unsigned CFIIndex;
731
732 if (HasBP) {
733 // Define CFA in terms of BP. Do this in preference to using FP/SP,
734 // because if the stack needed aligning then CFA won't be at a fixed
735 // offset from FP/SP.
736 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
737 CFIIndex = MMI.addFrameInst(
738 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
739 } else {
740 // Adjust the definition of CFA to account for the change in SP.
741 assert(NegFrameSize);
742 CFIIndex = MMI.addFrameInst(
743 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
744 }
735745 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
736746 .addCFIIndex(CFIIndex);
737747
738748 if (HasFP) {
749 // Describe where FP was saved, at a fixed offset from CFA.
739750 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
740751 CFIIndex = MMI.addFrameInst(
741752 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
744755 }
745756
746757 if (HasBP) {
758 // Describe where BP was saved, at a fixed offset from CFA.
747759 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
748760 CFIIndex = MMI.addFrameInst(
749761 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
752764 }
753765
754766 if (MustSaveLR) {
767 // Describe where LR was saved, at a fixed offset from CFA.
755768 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
756769 CFIIndex = MMI.addFrameInst(
757770 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
766779 .addReg(SPReg)
767780 .addReg(SPReg);
768781
769 if (needsFrameMoves) {
770 // Mark effective beginning of when frame pointer is ready.
782 if (!HasBP && needsCFI) {
783 // Change the definition of CFA from SP+offset to FP+offset, because SP
784 // will change at every alloca.
771785 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
772786 unsigned CFIIndex = MMI.addFrameInst(
773787 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
777791 }
778792 }
779793
780 if (needsFrameMoves) {
781 // Add callee saved registers to move list.
794 if (needsCFI) {
795 // Describe where callee saved registers were saved, at fixed offsets from
796 // CFA.
782797 const std::vector &CSI = MFI->getCalleeSavedInfo();
783798 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
784799 unsigned Reg = CSI[I].getReg();
3636 ; CHECK-DAG: subfic 0, [[REG]], -160
3737 ; CHECK: stdux 1, 1, 0
3838
39 ; CHECK: .cfi_def_cfa_register r30
3940 ; CHECK: .cfi_offset r30, -16
4041 ; CHECK: .cfi_offset lr, 16
4142
5859 ; CHECK-FP-DAG: subfic 0, [[REG]], -160
5960 ; CHECK-FP: stdux 1, 1, 0
6061
62 ; CHECK-FP: .cfi_def_cfa_register r30
6163 ; CHECK-FP: .cfi_offset r31, -8
6264 ; CHECK-FP: .cfi_offset r30, -16
6365 ; CHECK-FP: .cfi_offset lr, 16
118120 ; CHECK-DAG: std 0, 16(1)
119121 ; CHECK-DAG: subfc 0, [[REG3]], [[REG2]]
120122 ; CHECK: stdux 1, 1, 0
123
124 ; CHECK: .cfi_def_cfa_register r30
121125
122126 ; CHECK: blr
123127
177181 ; CHECK-DAG: subfic 0, [[REG]], -192
178182 ; CHECK: stdux 1, 1, 0
179183
184 ; CHECK: .cfi_def_cfa_register r30
185
180186 ; CHECK: stfd 30, -16(30)
181187
182188 ; CHECK: blr
192198 ; CHECK-FP-DAG: subfic 0, [[REG]], -192
193199 ; CHECK-FP: stdux 1, 1, 0
194200
201 ; CHECK-FP: .cfi_def_cfa_register r30
202
195203 ; CHECK-FP: stfd 30, -16(30)
196204
197205 ; CHECK-FP: blr