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AMDGPU: Whitespace fixes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285659 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 3 years ago
8 changed file(s) with 38 addition(s) and 40 deletion(s). Raw diff Collapse all Expand all
337337 Implies
338338 >;
339339
340 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
340 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
341341 [FeatureSeaIslands,
342342 FeatureLDSBankCount32]>;
343
343
344344 def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
345345 [FeatureSeaIslands,
346346 HalfRate64Ops,
347347 FeatureLDSBankCount32,
348348 FeatureFastFMAF32]>;
349
349
350350 def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
351351 [FeatureSeaIslands,
352352 FeatureLDSBankCount16,
353353 FeatureXNACK]>;
354
354
355355 def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0,
356356 [FeatureVolcanicIslands,
357357 FeatureLDSBankCount32,
358358 FeatureSGPRInitBug]>;
359
359
360360 def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
361361 [FeatureVolcanicIslands,
362362 FeatureLDSBankCount32,
363363 FeatureXNACK]>;
364
364
365365 def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
366366 [FeatureVolcanicIslands,
367367 FeatureLDSBankCount32,
368368 FeatureSGPRInitBug]>;
369
369
370370 def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
371371 [FeatureVolcanicIslands,
372372 FeatureLDSBankCount32]>;
373
373
374374 def FeatureISAVersion8_0_4 : SubtargetFeatureISAVersion <8,0,4,
375375 [FeatureVolcanicIslands,
376376 FeatureLDSBankCount32]>;
377
377
378378 def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
379379 [FeatureVolcanicIslands,
380380 FeatureLDSBankCount16,
215215 bool isImmTy(ImmTy ImmT) const {
216216 return isImm() && Imm.Type == ImmT;
217217 }
218
218
219219 bool isImmModifier() const {
220220 return isImm() && Imm.Type != ImmTyNone;
221221 }
222
222
223223 bool isClampSI() const { return isImmTy(ImmTyClampSI); }
224224 bool isOModSI() const { return isImmTy(ImmTyOModSI); }
225225 bool isDMask() const { return isImmTy(ImmTyDMask); }
244244 bool isSDWASrc0Sel() const { return isImmTy(ImmTySdwaSrc0Sel); }
245245 bool isSDWASrc1Sel() const { return isImmTy(ImmTySdwaSrc1Sel); }
246246 bool isSDWADstUnused() const { return isImmTy(ImmTySdwaDstUnused); }
247
247
248248 bool isMod() const {
249249 return isClampSI() || isOModSI();
250250 }
296296 bool isVCSrcB64() const {
297297 return isRegClass(AMDGPU::VS_64RegClassID) || isInlinableImm(MVT::i64);
298298 }
299
299
300300 bool isVCSrcF32() const {
301301 return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(MVT::f32);
302302 }
400400 bool hasModifiers() const {
401401 return getModifiers().hasModifiers();
402402 }
403
403
404404 bool hasFPModifiers() const {
405405 return getModifiers().hasFPModifiers();
406406 }
13441344 Parser.Lex();
13451345 Mods.Sext = true;
13461346 }
1347
1347
13481348 if (Mods.hasIntModifiers()) {
13491349 AMDGPUOperand &Op = static_cast(*Operands.back());
13501350 Op.setModifiers(Mods);
30123012 }
30133013
30143014 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
3015
3015
30163016 if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa) {
30173017 // V_NOP_sdwa has no optional sdwa arguments
30183018 switch (BasicInstType) {
30383038 llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");
30393039 }
30403040 }
3041
3041
30423042 // special case v_mac_f32:
30433043 // it has src2 register operand that is tied to dst operand
30443044 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa) {
129129 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
130130 i1imm:$slc, i1imm:$tfe, SCSrc_b32:$soffset),
131131 " $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"#
132 " $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset"
133 > {
132 " $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset"> {
134133 let mayLoad = 1;
135134 let mayStore = 0;
136135 }
141140 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
142141 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_b32:$soffset),
143142 " $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"#
144 " $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset"
145 > {
143 " $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset"> {
146144 let mayLoad = 0;
147145 let mayStore = 1;
148146 }
276274 string ret = Pfx # "$offset";
277275 }
278276
279 class MUBUF_SetupAddr {
277 class MUBUF_SetupAddr {
280278 bits<1> offen = !if(!eq(addrKind, BUFAddrKind.OffEn), 1,
281279 !if(!eq(addrKind, BUFAddrKind.BothEn), 1 , 0));
282280
9999 let AsmMatchConverter = "cvtDSOffset01";
100100 }
101101
102 class DS_1A2D_NORET
102 class DS_1A2D_NORET
103103 : DS_Pseudo
104104 (outs),
105105 (ins VGPR_32:$addr, rc:$data0, rc:$data1, offset:$offset, gds:$gds),
132132 }
133133
134134 class DS_1A2D_RET
135 RegisterClass rc = VGPR_32,
135 RegisterClass rc = VGPR_32,
136136 RegisterClass src = rc>
137137 : DS_Pseudo
138138 (outs rc:$vdst),
145145 class DS_1A_RET
146146 : DS_Pseudo
147147 (outs rc:$vdst),
148 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
148 (ins VGPR_32:$addr, offset:$offset, gds:$gds),
149149 "$vdst, $addr$offset$gds"> {
150150
151151 let has_data0 = 0;
206206 (ins VGPR_32:$addr),
207207 "$addr gds"> {
208208
209 let has_vdst = 0;
210 let has_data0 = 0;
209 let has_vdst = 0;
210 let has_data0 = 0;
211211 let has_data1 = 0;
212212 let has_offset = 0;
213213 let has_offset0 = 0;
214214 let has_offset1 = 0;
215215
216 let has_gds = 0;
216 let has_gds = 0;
217217 let gdsValue = 1;
218218 }
219219
748748 let AssemblerPredicates = [isVI];
749749 let DecoderNamespace="VI";
750750
751 // encoding
751 // encoding
752752 let Inst{7-0} = !if(ds.has_offset0, offset0, 0);
753753 let Inst{15-8} = !if(ds.has_offset1, offset1, 0);
754754 let Inst{16} = !if(ds.has_gds, gds, ds.gdsValue);
5757
5858 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
5959 return MCDisassembler::Success;
60 return addOperand(Inst, MCOperand::createImm(Imm));
60 return addOperand(Inst, MCOperand::createImm(Imm));
6161 }
6262
6363 #define DECODE_OPERAND2(RegClass, DecName) \
446446 //===----------------------------------------------------------------------===//
447447 // AMDGPUSymbolizer
448448 //===----------------------------------------------------------------------===//
449
449
450450 // Try to find symbol name for specified label
451451 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
452452 raw_ostream &/*cStream*/, int64_t Value,
481481 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
482482 LLVMOpInfoCallback /*GetOpInfo*/,
483483 LLVMSymbolLookupCallback /*SymbolLookUp*/,
484 void *DisInfo,
484 void *DisInfo,
485485 MCContext *Ctx,
486486 std::unique_ptr &&RelInfo) {
487487 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
103103
104104 public:
105105 AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr &&RelInfo,
106 void *disInfo)
106 void *disInfo)
107107 : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
108108
109109 bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
6464 // and can be retrieved by DAG->getPressureDif(SU).
6565 TempTracker.getUpwardPressure(SU->getInstr(), Pressure, MaxPressure);
6666 }
67
67
6868 int NewSGPRPressure = Pressure[SRI->getSGPRPressureSet()];
6969 int NewVGPRPressure = Pressure[SRI->getVGPRPressureSet()];
7070
234234 TopCand.Reason = NoCand;
235235 GenericScheduler::tryCandidate(Cand, TopCand, nullptr);
236236 if (TopCand.Reason != NoCand) {
237 Cand.setBest(TopCand);
237 Cand.setBest(TopCand);
238238 } else {
239239 TopCand.Reason = TopReason;
240240 }
364364
365365 multiclass SIRegOperand {
366366 let OperandNamespace = "AMDGPU" in {
367
367
368368 def _b32 : RegisterOperand(rc#"_32")> {
369369 let OperandType = opType#"_INT";
370370 let ParserMatchClass = RegImmMatcher;
371371 }
372
372
373373 def _f32 : RegisterOperand(rc#"_32")> {
374374 let OperandType = opType#"_FP";
375375 let ParserMatchClass = RegImmMatcher;
376376 }
377
377
378378 def _b64 : RegisterOperand(rc#"_64")> {
379379 let OperandType = opType#"_INT";
380380 let ParserMatchClass = RegImmMatcher;
387387 }
388388 }
389389
390 multiclass RegImmOperand
390 multiclass RegImmOperand
391391 : SIRegOperand;
392392
393 multiclass RegInlineOperand
393 multiclass RegInlineOperand
394394 : SIRegOperand;
395395
396396 //===----------------------------------------------------------------------===//