llvm.org GIT mirror llvm / 7764ab8
[GlobalISel][X86_64] Support for G_FPTOSI Differential Revision: https://reviews.llvm.org/D49183 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341200 91177308-0d34-0410-b5e6-96231b3b80d8 Alexander Ivchenko 1 year, 11 months ago
5 changed file(s) with 906 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
218218 .clampScalar(0, s32, s64)
219219 .widenScalarToNextPow2(0);
220220
221 getActionDefinitionsBuilder(G_FPTOSI)
222 .legalForCartesianProduct({s32, s64})
223 .clampScalar(1, s32, s64)
224 .widenScalarToNextPow2(0)
225 .clampScalar(0, s32, s64)
226 .widenScalarToNextPow2(1);
227
221228 // Comparison
222229 setAction({G_ICMP, 1, s64}, Legal);
223230
197197 // Instruction having only floating-point operands (all scalars in VECRReg)
198198 getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx);
199199 break;
200 case TargetOpcode::G_SITOFP: {
200 case TargetOpcode::G_SITOFP:
201 case TargetOpcode::G_FPTOSI: {
201202 // Some of the floating-point instructions have mixed GPR and FP operands:
202203 // fine-tune the computed mapping.
203204 auto &Op0 = MI.getOperand(0);
204205 auto &Op1 = MI.getOperand(1);
205206 const LLT Ty0 = MRI.getType(Op0.getReg());
206207 const LLT Ty1 = MRI.getType(Op1.getReg());
207 OpRegBankIdx[0] = getPartialMappingIdx(Ty0, /* isFP */ true);
208 OpRegBankIdx[1] = getPartialMappingIdx(Ty1, /* isFP */ false);
208
209 bool FirstArgIsFP = Opc == TargetOpcode::G_SITOFP;
210 bool SecondArgIsFP = Opc == TargetOpcode::G_FPTOSI;
211 OpRegBankIdx[0] = getPartialMappingIdx(Ty0, /* isFP */ FirstArgIsFP);
212 OpRegBankIdx[1] = getPartialMappingIdx(Ty1, /* isFP */ SecondArgIsFP);
209213 break;
210214 }
211215 case TargetOpcode::G_FCMP: {
263263 entry:
264264 %conv = sitofp i64 %a to double
265265 ret double %conv
266 }
267
268 define signext i8 @float_to_int8(float %val) {
269 entry:
270 %conv = fptosi float %val to i8
271 ret i8 %conv
272 }
273
274 define signext i16 @float_to_int16(float %val) {
275 entry:
276 %conv = fptosi float %val to i16
277 ret i16 %conv
278 }
279
280 define i32 @float_to_int32(float %val) {
281 entry:
282 %conv = fptosi float %val to i32
283 ret i32 %conv
284 }
285
286 define i64 @float_to_int64(float %val) {
287 entry:
288 %conv = fptosi float %val to i64
289 ret i64 %conv
290 }
291
292 define signext i8 @double_to_int8(double %val) {
293 entry:
294 %conv = fptosi double %val to i8
295 ret i8 %conv
296 }
297
298 define signext i16 @double_to_int16(double %val) {
299 entry:
300 %conv = fptosi double %val to i16
301 ret i16 %conv
302 }
303
304 define i32 @double_to_int32(double %val) {
305 entry:
306 %conv = fptosi double %val to i32
307 ret i32 %conv
308 }
309
310 define i64 @double_to_int64(double %val) {
311 entry:
312 %conv = fptosi double %val to i64
313 ret i64 %conv
266314 }
267315
268316 define i1 @fcmp_float_oeq(float %x, float %y) {
21192167
21202168 ...
21212169 ---
2170 name: float_to_int8
2171 alignment: 4
2172 legalized: true
2173 tracksRegLiveness: true
2174 registers:
2175 - { id: 0, class: _ }
2176 - { id: 1, class: _ }
2177 - { id: 2, class: _ }
2178 - { id: 3, class: _ }
2179 body: |
2180 bb.1.entry:
2181 liveins: $xmm0
2182
2183 ; FAST-LABEL: name: float_to_int8
2184 ; FAST: liveins: $xmm0
2185 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2186 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
2187 ; FAST: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[TRUNC]](s32)
2188 ; FAST: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[FPTOSI]](s32)
2189 ; FAST: $al = COPY [[TRUNC1]](s8)
2190 ; FAST: RET 0, implicit $al
2191 ; GREEDY-LABEL: name: float_to_int8
2192 ; GREEDY: liveins: $xmm0
2193 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2194 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
2195 ; GREEDY: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[TRUNC]](s32)
2196 ; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[FPTOSI]](s32)
2197 ; GREEDY: $al = COPY [[TRUNC1]](s8)
2198 ; GREEDY: RET 0, implicit $al
2199 %1:_(s128) = COPY $xmm0
2200 %0:_(s32) = G_TRUNC %1(s128)
2201 %3:_(s32) = G_FPTOSI %0(s32)
2202 %2:_(s8) = G_TRUNC %3(s32)
2203 $al = COPY %2(s8)
2204 RET 0, implicit $al
2205
2206 ...
2207 ---
2208 name: float_to_int16
2209 alignment: 4
2210 legalized: true
2211 tracksRegLiveness: true
2212 registers:
2213 - { id: 0, class: _ }
2214 - { id: 1, class: _ }
2215 - { id: 2, class: _ }
2216 - { id: 3, class: _ }
2217 body: |
2218 bb.1.entry:
2219 liveins: $xmm0
2220
2221 ; FAST-LABEL: name: float_to_int16
2222 ; FAST: liveins: $xmm0
2223 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2224 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
2225 ; FAST: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[TRUNC]](s32)
2226 ; FAST: [[TRUNC1:%[0-9]+]]:gpr(s16) = G_TRUNC [[FPTOSI]](s32)
2227 ; FAST: $ax = COPY [[TRUNC1]](s16)
2228 ; FAST: RET 0, implicit $ax
2229 ; GREEDY-LABEL: name: float_to_int16
2230 ; GREEDY: liveins: $xmm0
2231 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2232 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
2233 ; GREEDY: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[TRUNC]](s32)
2234 ; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s16) = G_TRUNC [[FPTOSI]](s32)
2235 ; GREEDY: $ax = COPY [[TRUNC1]](s16)
2236 ; GREEDY: RET 0, implicit $ax
2237 %1:_(s128) = COPY $xmm0
2238 %0:_(s32) = G_TRUNC %1(s128)
2239 %3:_(s32) = G_FPTOSI %0(s32)
2240 %2:_(s16) = G_TRUNC %3(s32)
2241 $ax = COPY %2(s16)
2242 RET 0, implicit $ax
2243
2244 ...
2245 ---
2246 name: float_to_int32
2247 alignment: 4
2248 legalized: true
2249 tracksRegLiveness: true
2250 registers:
2251 - { id: 0, class: _ }
2252 - { id: 1, class: _ }
2253 - { id: 2, class: _ }
2254 body: |
2255 bb.1.entry:
2256 liveins: $xmm0
2257
2258 ; FAST-LABEL: name: float_to_int32
2259 ; FAST: liveins: $xmm0
2260 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2261 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
2262 ; FAST: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[TRUNC]](s32)
2263 ; FAST: $eax = COPY [[FPTOSI]](s32)
2264 ; FAST: RET 0, implicit $eax
2265 ; GREEDY-LABEL: name: float_to_int32
2266 ; GREEDY: liveins: $xmm0
2267 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2268 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
2269 ; GREEDY: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[TRUNC]](s32)
2270 ; GREEDY: $eax = COPY [[FPTOSI]](s32)
2271 ; GREEDY: RET 0, implicit $eax
2272 %1:_(s128) = COPY $xmm0
2273 %0:_(s32) = G_TRUNC %1(s128)
2274 %2:_(s32) = G_FPTOSI %0(s32)
2275 $eax = COPY %2(s32)
2276 RET 0, implicit $eax
2277
2278 ...
2279 ---
2280 name: float_to_int64
2281 alignment: 4
2282 legalized: true
2283 tracksRegLiveness: true
2284 registers:
2285 - { id: 0, class: _ }
2286 - { id: 1, class: _ }
2287 - { id: 2, class: _ }
2288 body: |
2289 bb.1.entry:
2290 liveins: $xmm0
2291
2292 ; FAST-LABEL: name: float_to_int64
2293 ; FAST: liveins: $xmm0
2294 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2295 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
2296 ; FAST: [[FPTOSI:%[0-9]+]]:gpr(s64) = G_FPTOSI [[TRUNC]](s32)
2297 ; FAST: $rax = COPY [[FPTOSI]](s64)
2298 ; FAST: RET 0, implicit $rax
2299 ; GREEDY-LABEL: name: float_to_int64
2300 ; GREEDY: liveins: $xmm0
2301 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2302 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
2303 ; GREEDY: [[FPTOSI:%[0-9]+]]:gpr(s64) = G_FPTOSI [[TRUNC]](s32)
2304 ; GREEDY: $rax = COPY [[FPTOSI]](s64)
2305 ; GREEDY: RET 0, implicit $rax
2306 %1:_(s128) = COPY $xmm0
2307 %0:_(s32) = G_TRUNC %1(s128)
2308 %2:_(s64) = G_FPTOSI %0(s32)
2309 $rax = COPY %2(s64)
2310 RET 0, implicit $rax
2311
2312 ...
2313 ---
2314 name: double_to_int8
2315 alignment: 4
2316 legalized: true
2317 tracksRegLiveness: true
2318 registers:
2319 - { id: 0, class: _ }
2320 - { id: 1, class: _ }
2321 - { id: 2, class: _ }
2322 - { id: 3, class: _ }
2323 body: |
2324 bb.1.entry:
2325 liveins: $xmm0
2326
2327 ; FAST-LABEL: name: double_to_int8
2328 ; FAST: liveins: $xmm0
2329 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2330 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
2331 ; FAST: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[TRUNC]](s64)
2332 ; FAST: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[FPTOSI]](s32)
2333 ; FAST: $al = COPY [[TRUNC1]](s8)
2334 ; FAST: RET 0, implicit $al
2335 ; GREEDY-LABEL: name: double_to_int8
2336 ; GREEDY: liveins: $xmm0
2337 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2338 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
2339 ; GREEDY: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[TRUNC]](s64)
2340 ; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[FPTOSI]](s32)
2341 ; GREEDY: $al = COPY [[TRUNC1]](s8)
2342 ; GREEDY: RET 0, implicit $al
2343 %1:_(s128) = COPY $xmm0
2344 %0:_(s64) = G_TRUNC %1(s128)
2345 %3:_(s32) = G_FPTOSI %0(s64)
2346 %2:_(s8) = G_TRUNC %3(s32)
2347 $al = COPY %2(s8)
2348 RET 0, implicit $al
2349
2350 ...
2351 ---
2352 name: double_to_int16
2353 alignment: 4
2354 legalized: true
2355 tracksRegLiveness: true
2356 registers:
2357 - { id: 0, class: _ }
2358 - { id: 1, class: _ }
2359 - { id: 2, class: _ }
2360 - { id: 3, class: _ }
2361 body: |
2362 bb.1.entry:
2363 liveins: $xmm0
2364
2365 ; FAST-LABEL: name: double_to_int16
2366 ; FAST: liveins: $xmm0
2367 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2368 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
2369 ; FAST: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[TRUNC]](s64)
2370 ; FAST: [[TRUNC1:%[0-9]+]]:gpr(s16) = G_TRUNC [[FPTOSI]](s32)
2371 ; FAST: $ax = COPY [[TRUNC1]](s16)
2372 ; FAST: RET 0, implicit $ax
2373 ; GREEDY-LABEL: name: double_to_int16
2374 ; GREEDY: liveins: $xmm0
2375 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2376 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
2377 ; GREEDY: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[TRUNC]](s64)
2378 ; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s16) = G_TRUNC [[FPTOSI]](s32)
2379 ; GREEDY: $ax = COPY [[TRUNC1]](s16)
2380 ; GREEDY: RET 0, implicit $ax
2381 %1:_(s128) = COPY $xmm0
2382 %0:_(s64) = G_TRUNC %1(s128)
2383 %3:_(s32) = G_FPTOSI %0(s64)
2384 %2:_(s16) = G_TRUNC %3(s32)
2385 $ax = COPY %2(s16)
2386 RET 0, implicit $ax
2387
2388 ...
2389 ---
2390 name: double_to_int32
2391 alignment: 4
2392 legalized: true
2393 tracksRegLiveness: true
2394 registers:
2395 - { id: 0, class: _ }
2396 - { id: 1, class: _ }
2397 - { id: 2, class: _ }
2398 body: |
2399 bb.1.entry:
2400 liveins: $xmm0
2401
2402 ; FAST-LABEL: name: double_to_int32
2403 ; FAST: liveins: $xmm0
2404 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2405 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
2406 ; FAST: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[TRUNC]](s64)
2407 ; FAST: $eax = COPY [[FPTOSI]](s32)
2408 ; FAST: RET 0, implicit $eax
2409 ; GREEDY-LABEL: name: double_to_int32
2410 ; GREEDY: liveins: $xmm0
2411 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2412 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
2413 ; GREEDY: [[FPTOSI:%[0-9]+]]:gpr(s32) = G_FPTOSI [[TRUNC]](s64)
2414 ; GREEDY: $eax = COPY [[FPTOSI]](s32)
2415 ; GREEDY: RET 0, implicit $eax
2416 %1:_(s128) = COPY $xmm0
2417 %0:_(s64) = G_TRUNC %1(s128)
2418 %2:_(s32) = G_FPTOSI %0(s64)
2419 $eax = COPY %2(s32)
2420 RET 0, implicit $eax
2421
2422 ...
2423 ---
2424 name: double_to_int64
2425 alignment: 4
2426 legalized: true
2427 tracksRegLiveness: true
2428 registers:
2429 - { id: 0, class: _ }
2430 - { id: 1, class: _ }
2431 - { id: 2, class: _ }
2432 body: |
2433 bb.1.entry:
2434 liveins: $xmm0
2435
2436 ; FAST-LABEL: name: double_to_int64
2437 ; FAST: liveins: $xmm0
2438 ; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2439 ; FAST: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
2440 ; FAST: [[FPTOSI:%[0-9]+]]:gpr(s64) = G_FPTOSI [[TRUNC]](s64)
2441 ; FAST: $rax = COPY [[FPTOSI]](s64)
2442 ; FAST: RET 0, implicit $rax
2443 ; GREEDY-LABEL: name: double_to_int64
2444 ; GREEDY: liveins: $xmm0
2445 ; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
2446 ; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
2447 ; GREEDY: [[FPTOSI:%[0-9]+]]:gpr(s64) = G_FPTOSI [[TRUNC]](s64)
2448 ; GREEDY: $rax = COPY [[FPTOSI]](s64)
2449 ; GREEDY: RET 0, implicit $rax
2450 %1:_(s128) = COPY $xmm0
2451 %0:_(s64) = G_TRUNC %1(s128)
2452 %2:_(s64) = G_FPTOSI %0(s64)
2453 $rax = COPY %2(s64)
2454 RET 0, implicit $rax
2455
2456 ...
2457 ---
21222458 name: fcmp_float_oeq
21232459 alignment: 4
21242460 legalized: true
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
2
3 --- |
4
5 define signext i8 @float_to_int8(float %val) {
6 entry:
7 %conv = fptosi float %val to i8
8 ret i8 %conv
9 }
10
11 define signext i16 @float_to_int16(float %val) {
12 entry:
13 %conv = fptosi float %val to i16
14 ret i16 %conv
15 }
16
17 define i32 @float_to_int32(float %val) {
18 entry:
19 %conv = fptosi float %val to i32
20 ret i32 %conv
21 }
22
23 define i64 @float_to_int64(float %val) {
24 entry:
25 %conv = fptosi float %val to i64
26 ret i64 %conv
27 }
28
29 define signext i8 @double_to_int8(double %val) {
30 entry:
31 %conv = fptosi double %val to i8
32 ret i8 %conv
33 }
34
35 define signext i16 @double_to_int16(double %val) {
36 entry:
37 %conv = fptosi double %val to i16
38 ret i16 %conv
39 }
40
41 define i32 @double_to_int32(double %val) {
42 entry:
43 %conv = fptosi double %val to i32
44 ret i32 %conv
45 }
46
47 define i64 @double_to_int64(double %val) {
48 entry:
49 %conv = fptosi double %val to i64
50 ret i64 %conv
51 }
52
53 ...
54 ---
55 name: float_to_int8
56 alignment: 4
57 tracksRegLiveness: true
58 registers:
59 - { id: 0, class: _ }
60 - { id: 1, class: _ }
61 - { id: 2, class: _ }
62 body: |
63 bb.1.entry:
64 liveins: $xmm0
65
66 ; CHECK-LABEL: name: float_to_int8
67 ; CHECK: liveins: $xmm0
68 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
69 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
70 ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s32)
71 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[FPTOSI]](s32)
72 ; CHECK: $al = COPY [[TRUNC1]](s8)
73 ; CHECK: RET 0, implicit $al
74 %1:_(s128) = COPY $xmm0
75 %0:_(s32) = G_TRUNC %1(s128)
76 %2:_(s8) = G_FPTOSI %0(s32)
77 $al = COPY %2(s8)
78 RET 0, implicit $al
79
80 ...
81 ---
82 name: float_to_int16
83 alignment: 4
84 tracksRegLiveness: true
85 registers:
86 - { id: 0, class: _ }
87 - { id: 1, class: _ }
88 - { id: 2, class: _ }
89 body: |
90 bb.1.entry:
91 liveins: $xmm0
92
93 ; CHECK-LABEL: name: float_to_int16
94 ; CHECK: liveins: $xmm0
95 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
96 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
97 ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s32)
98 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[FPTOSI]](s32)
99 ; CHECK: $ax = COPY [[TRUNC1]](s16)
100 ; CHECK: RET 0, implicit $ax
101 %1:_(s128) = COPY $xmm0
102 %0:_(s32) = G_TRUNC %1(s128)
103 %2:_(s16) = G_FPTOSI %0(s32)
104 $ax = COPY %2(s16)
105 RET 0, implicit $ax
106
107 ...
108 ---
109 name: float_to_int32
110 alignment: 4
111 tracksRegLiveness: true
112 registers:
113 - { id: 0, class: _ }
114 - { id: 1, class: _ }
115 - { id: 2, class: _ }
116 body: |
117 bb.1.entry:
118 liveins: $xmm0
119
120 ; CHECK-LABEL: name: float_to_int32
121 ; CHECK: liveins: $xmm0
122 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
123 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
124 ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s32)
125 ; CHECK: $eax = COPY [[FPTOSI]](s32)
126 ; CHECK: RET 0, implicit $eax
127 %1:_(s128) = COPY $xmm0
128 %0:_(s32) = G_TRUNC %1(s128)
129 %2:_(s32) = G_FPTOSI %0(s32)
130 $eax = COPY %2(s32)
131 RET 0, implicit $eax
132
133 ...
134 ---
135 name: float_to_int64
136 alignment: 4
137 tracksRegLiveness: true
138 registers:
139 - { id: 0, class: _ }
140 - { id: 1, class: _ }
141 - { id: 2, class: _ }
142 body: |
143 bb.1.entry:
144 liveins: $xmm0
145
146 ; CHECK-LABEL: name: float_to_int64
147 ; CHECK: liveins: $xmm0
148 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
149 ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s128)
150 ; CHECK: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[TRUNC]](s32)
151 ; CHECK: $rax = COPY [[FPTOSI]](s64)
152 ; CHECK: RET 0, implicit $rax
153 %1:_(s128) = COPY $xmm0
154 %0:_(s32) = G_TRUNC %1(s128)
155 %2:_(s64) = G_FPTOSI %0(s32)
156 $rax = COPY %2(s64)
157 RET 0, implicit $rax
158
159 ...
160 ---
161 name: double_to_int8
162 alignment: 4
163 tracksRegLiveness: true
164 registers:
165 - { id: 0, class: _ }
166 - { id: 1, class: _ }
167 - { id: 2, class: _ }
168 body: |
169 bb.1.entry:
170 liveins: $xmm0
171
172 ; CHECK-LABEL: name: double_to_int8
173 ; CHECK: liveins: $xmm0
174 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
175 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
176 ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s64)
177 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[FPTOSI]](s32)
178 ; CHECK: $al = COPY [[TRUNC1]](s8)
179 ; CHECK: RET 0, implicit $al
180 %1:_(s128) = COPY $xmm0
181 %0:_(s64) = G_TRUNC %1(s128)
182 %2:_(s8) = G_FPTOSI %0(s64)
183 $al = COPY %2(s8)
184 RET 0, implicit $al
185
186 ...
187 ---
188 name: double_to_int16
189 alignment: 4
190 tracksRegLiveness: true
191 registers:
192 - { id: 0, class: _ }
193 - { id: 1, class: _ }
194 - { id: 2, class: _ }
195 body: |
196 bb.1.entry:
197 liveins: $xmm0
198
199 ; CHECK-LABEL: name: double_to_int16
200 ; CHECK: liveins: $xmm0
201 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
202 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
203 ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s64)
204 ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[FPTOSI]](s32)
205 ; CHECK: $ax = COPY [[TRUNC1]](s16)
206 ; CHECK: RET 0, implicit $ax
207 %1:_(s128) = COPY $xmm0
208 %0:_(s64) = G_TRUNC %1(s128)
209 %2:_(s16) = G_FPTOSI %0(s64)
210 $ax = COPY %2(s16)
211 RET 0, implicit $ax
212
213 ...
214 ---
215 name: double_to_int32
216 alignment: 4
217 tracksRegLiveness: true
218 registers:
219 - { id: 0, class: _ }
220 - { id: 1, class: _ }
221 - { id: 2, class: _ }
222 body: |
223 bb.1.entry:
224 liveins: $xmm0
225
226 ; CHECK-LABEL: name: double_to_int32
227 ; CHECK: liveins: $xmm0
228 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
229 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
230 ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s64)
231 ; CHECK: $eax = COPY [[FPTOSI]](s32)
232 ; CHECK: RET 0, implicit $eax
233 %1:_(s128) = COPY $xmm0
234 %0:_(s64) = G_TRUNC %1(s128)
235 %2:_(s32) = G_FPTOSI %0(s64)
236 $eax = COPY %2(s32)
237 RET 0, implicit $eax
238
239 ...
240 ---
241 name: double_to_int64
242 alignment: 4
243 tracksRegLiveness: true
244 registers:
245 - { id: 0, class: _ }
246 - { id: 1, class: _ }
247 - { id: 2, class: _ }
248 body: |
249 bb.1.entry:
250 liveins: $xmm0
251
252 ; CHECK-LABEL: name: double_to_int64
253 ; CHECK: liveins: $xmm0
254 ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $xmm0
255 ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s128)
256 ; CHECK: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[TRUNC]](s64)
257 ; CHECK: $rax = COPY [[FPTOSI]](s64)
258 ; CHECK: RET 0, implicit $rax
259 %1:_(s128) = COPY $xmm0
260 %0:_(s64) = G_TRUNC %1(s128)
261 %2:_(s64) = G_FPTOSI %0(s64)
262 $rax = COPY %2(s64)
263 RET 0, implicit $rax
264
265 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
2
3 --- |
4
5 define signext i8 @float_to_int8(float %val) {
6 entry:
7 %conv = fptosi float %val to i8
8 ret i8 %conv
9 }
10
11 define signext i16 @float_to_int16(float %val) {
12 entry:
13 %conv = fptosi float %val to i16
14 ret i16 %conv
15 }
16
17 define i32 @float_to_int32(float %val) {
18 entry:
19 %conv = fptosi float %val to i32
20 ret i32 %conv
21 }
22
23 define i64 @float_to_int64(float %val) {
24 entry:
25 %conv = fptosi float %val to i64
26 ret i64 %conv
27 }
28
29 define signext i8 @double_to_int8(double %val) {
30 entry:
31 %conv = fptosi double %val to i8
32 ret i8 %conv
33 }
34
35 define signext i16 @double_to_int16(double %val) {
36 entry:
37 %conv = fptosi double %val to i16
38 ret i16 %conv
39 }
40
41 define i32 @double_to_int32(double %val) {
42 entry:
43 %conv = fptosi double %val to i32
44 ret i32 %conv
45 }
46
47 define i64 @double_to_int64(double %val) {
48 entry:
49 %conv = fptosi double %val to i64
50 ret i64 %conv
51 }
52
53 ...
54 ---
55 name: float_to_int8
56 alignment: 4
57 legalized: true
58 regBankSelected: true
59 tracksRegLiveness: true
60 registers:
61 - { id: 0, class: vecr }
62 - { id: 1, class: vecr }
63 - { id: 2, class: gpr }
64 - { id: 3, class: gpr }
65 body: |
66 bb.1.entry:
67 liveins: $xmm0
68
69 ; CHECK-LABEL: name: float_to_int8
70 ; CHECK: liveins: $xmm0
71 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
72 ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
73 ; CHECK: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = CVTTSS2SIrr [[COPY1]]
74 ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[CVTTSS2SIrr]].sub_8bit
75 ; CHECK: $al = COPY [[COPY2]]
76 ; CHECK: RET 0, implicit $al
77 %1:vecr(s128) = COPY $xmm0
78 %0:vecr(s32) = G_TRUNC %1(s128)
79 %3:gpr(s32) = G_FPTOSI %0(s32)
80 %2:gpr(s8) = G_TRUNC %3(s32)
81 $al = COPY %2(s8)
82 RET 0, implicit $al
83
84 ...
85 ---
86 name: float_to_int16
87 alignment: 4
88 legalized: true
89 regBankSelected: true
90 tracksRegLiveness: true
91 registers:
92 - { id: 0, class: vecr }
93 - { id: 1, class: vecr }
94 - { id: 2, class: gpr }
95 - { id: 3, class: gpr }
96 body: |
97 bb.1.entry:
98 liveins: $xmm0
99
100 ; CHECK-LABEL: name: float_to_int16
101 ; CHECK: liveins: $xmm0
102 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
103 ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
104 ; CHECK: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = CVTTSS2SIrr [[COPY1]]
105 ; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY [[CVTTSS2SIrr]].sub_16bit
106 ; CHECK: $ax = COPY [[COPY2]]
107 ; CHECK: RET 0, implicit $ax
108 %1:vecr(s128) = COPY $xmm0
109 %0:vecr(s32) = G_TRUNC %1(s128)
110 %3:gpr(s32) = G_FPTOSI %0(s32)
111 %2:gpr(s16) = G_TRUNC %3(s32)
112 $ax = COPY %2(s16)
113 RET 0, implicit $ax
114
115 ...
116 ---
117 name: float_to_int32
118 alignment: 4
119 legalized: true
120 regBankSelected: true
121 tracksRegLiveness: true
122 registers:
123 - { id: 0, class: vecr }
124 - { id: 1, class: vecr }
125 - { id: 2, class: gpr }
126 body: |
127 bb.1.entry:
128 liveins: $xmm0
129
130 ; CHECK-LABEL: name: float_to_int32
131 ; CHECK: liveins: $xmm0
132 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
133 ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
134 ; CHECK: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = CVTTSS2SIrr [[COPY1]]
135 ; CHECK: $eax = COPY [[CVTTSS2SIrr]]
136 ; CHECK: RET 0, implicit $eax
137 %1:vecr(s128) = COPY $xmm0
138 %0:vecr(s32) = G_TRUNC %1(s128)
139 %2:gpr(s32) = G_FPTOSI %0(s32)
140 $eax = COPY %2(s32)
141 RET 0, implicit $eax
142
143 ...
144 ---
145 name: float_to_int64
146 alignment: 4
147 legalized: true
148 regBankSelected: true
149 tracksRegLiveness: true
150 registers:
151 - { id: 0, class: vecr }
152 - { id: 1, class: vecr }
153 - { id: 2, class: gpr }
154 body: |
155 bb.1.entry:
156 liveins: $xmm0
157
158 ; CHECK-LABEL: name: float_to_int64
159 ; CHECK: liveins: $xmm0
160 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
161 ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
162 ; CHECK: [[CVTTSS2SI64rr:%[0-9]+]]:gr64 = CVTTSS2SI64rr [[COPY1]]
163 ; CHECK: $rax = COPY [[CVTTSS2SI64rr]]
164 ; CHECK: RET 0, implicit $rax
165 %1:vecr(s128) = COPY $xmm0
166 %0:vecr(s32) = G_TRUNC %1(s128)
167 %2:gpr(s64) = G_FPTOSI %0(s32)
168 $rax = COPY %2(s64)
169 RET 0, implicit $rax
170
171 ...
172 ---
173 name: double_to_int8
174 alignment: 4
175 legalized: true
176 regBankSelected: true
177 tracksRegLiveness: true
178 registers:
179 - { id: 0, class: vecr }
180 - { id: 1, class: vecr }
181 - { id: 2, class: gpr }
182 - { id: 3, class: gpr }
183 body: |
184 bb.1.entry:
185 liveins: $xmm0
186
187 ; CHECK-LABEL: name: double_to_int8
188 ; CHECK: liveins: $xmm0
189 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
190 ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
191 ; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr [[COPY1]]
192 ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[CVTTSD2SIrr]].sub_8bit
193 ; CHECK: $al = COPY [[COPY2]]
194 ; CHECK: RET 0, implicit $al
195 %1:vecr(s128) = COPY $xmm0
196 %0:vecr(s64) = G_TRUNC %1(s128)
197 %3:gpr(s32) = G_FPTOSI %0(s64)
198 %2:gpr(s8) = G_TRUNC %3(s32)
199 $al = COPY %2(s8)
200 RET 0, implicit $al
201
202 ...
203 ---
204 name: double_to_int16
205 alignment: 4
206 legalized: true
207 regBankSelected: true
208 tracksRegLiveness: true
209 registers:
210 - { id: 0, class: vecr }
211 - { id: 1, class: vecr }
212 - { id: 2, class: gpr }
213 - { id: 3, class: gpr }
214 body: |
215 bb.1.entry:
216 liveins: $xmm0
217
218 ; CHECK-LABEL: name: double_to_int16
219 ; CHECK: liveins: $xmm0
220 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
221 ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
222 ; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr [[COPY1]]
223 ; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY [[CVTTSD2SIrr]].sub_16bit
224 ; CHECK: $ax = COPY [[COPY2]]
225 ; CHECK: RET 0, implicit $ax
226 %1:vecr(s128) = COPY $xmm0
227 %0:vecr(s64) = G_TRUNC %1(s128)
228 %3:gpr(s32) = G_FPTOSI %0(s64)
229 %2:gpr(s16) = G_TRUNC %3(s32)
230 $ax = COPY %2(s16)
231 RET 0, implicit $ax
232
233 ...
234 ---
235 name: double_to_int32
236 alignment: 4
237 legalized: true
238 regBankSelected: true
239 tracksRegLiveness: true
240 registers:
241 - { id: 0, class: vecr }
242 - { id: 1, class: vecr }
243 - { id: 2, class: gpr }
244 body: |
245 bb.1.entry:
246 liveins: $xmm0
247
248 ; CHECK-LABEL: name: double_to_int32
249 ; CHECK: liveins: $xmm0
250 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
251 ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
252 ; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr [[COPY1]]
253 ; CHECK: $eax = COPY [[CVTTSD2SIrr]]
254 ; CHECK: RET 0, implicit $eax
255 %1:vecr(s128) = COPY $xmm0
256 %0:vecr(s64) = G_TRUNC %1(s128)
257 %2:gpr(s32) = G_FPTOSI %0(s64)
258 $eax = COPY %2(s32)
259 RET 0, implicit $eax
260
261 ...
262 ---
263 name: double_to_int64
264 alignment: 4
265 legalized: true
266 regBankSelected: true
267 tracksRegLiveness: true
268 registers:
269 - { id: 0, class: vecr }
270 - { id: 1, class: vecr }
271 - { id: 2, class: gpr }
272 body: |
273 bb.1.entry:
274 liveins: $xmm0
275
276 ; CHECK-LABEL: name: double_to_int64
277 ; CHECK: liveins: $xmm0
278 ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
279 ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
280 ; CHECK: [[CVTTSD2SI64rr:%[0-9]+]]:gr64 = CVTTSD2SI64rr [[COPY1]]
281 ; CHECK: $rax = COPY [[CVTTSD2SI64rr]]
282 ; CHECK: RET 0, implicit $rax
283 %1:vecr(s128) = COPY $xmm0
284 %0:vecr(s64) = G_TRUNC %1(s128)
285 %2:gpr(s64) = G_FPTOSI %0(s64)
286 $rax = COPY %2(s64)
287 RET 0, implicit $rax
288
289 ...