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Generalize opcode selection in ARMBaseRegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8 David Goodwin 11 years ago
12 changed file(s) with 80 addition(s) and 63 deletion(s). Raw diff Collapse all Expand all
168168 BR_JTr,
169169 BR_JTm,
170170 BR_JTadd,
171 BX_RET,
171172 FCPYS,
172173 FCPYD,
173174 FLDD,
152152 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
153153 TII(tii), STI(sti),
154154 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
155 }
156
157 unsigned ARMBaseRegisterInfo::
158 getOpcode(int Op) const {
159 return TII.getOpcode((ARMII::Op)Op);
155160 }
156161
157162 const unsigned*
877882 void ARMBaseRegisterInfo::
878883 emitLoadConstPool(MachineBasicBlock &MBB,
879884 MachineBasicBlock::iterator &MBBI,
880 const TargetInstrInfo *TII, DebugLoc dl,
885 DebugLoc dl,
881886 unsigned DestReg, int Val,
882887 ARMCC::CondCodes Pred,
883888 unsigned PredReg) const {
886891 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
887892 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
888893
889 BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg)
894 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp), DestReg)
890895 .addConstantPoolIndex(Idx)
891896 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
892897 }
922927 MachineBasicBlock::iterator &MBBI,
923928 unsigned DestReg, unsigned BaseReg, int NumBytes,
924929 ARMCC::CondCodes Pred, unsigned PredReg,
925 const TargetInstrInfo &TII,
930 const ARMBaseInstrInfo &TII,
926931 DebugLoc dl) {
927932 bool isSub = NumBytes < 0;
928933 if (isSub) NumBytes = -NumBytes;
940945 assert(SOImmVal != -1 && "Bit extraction didn't work?");
941946
942947 // Build the new ADD / SUB.
943 BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
948 BuildMI(MBB, MBBI, dl, TII.get(TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri)), DestReg)
944949 .addReg(BaseReg, RegState::Kill).addImm(SOImmVal)
945950 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
946951 BaseReg = DestReg;
949954
950955 static void
951956 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
952 const TargetInstrInfo &TII, DebugLoc dl,
957 const ARMBaseInstrInfo &TII, DebugLoc dl,
953958 int NumBytes,
954959 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
955960 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
10491054 if (Opcode == ARM::INLINEASM)
10501055 AddrMode = ARMII::AddrMode2;
10511056
1052 if (Opcode == ARM::ADDri) {
1057 if (Opcode == getOpcode(ARMII::ADDri)) {
10531058 Offset += MI.getOperand(i+1).getImm();
10541059 if (Offset == 0) {
10551060 // Turn it into a move.
1056 MI.setDesc(TII.get(ARM::MOVr));
1061 MI.setDesc(TII.get(getOpcode(ARMII::MOVr)));
10571062 MI.getOperand(i).ChangeToRegister(FrameReg, false);
10581063 MI.RemoveOperand(i+1);
10591064 return;
10601065 } else if (Offset < 0) {
10611066 Offset = -Offset;
10621067 isSub = true;
1063 MI.setDesc(TII.get(ARM::SUBri));
1068 MI.setDesc(TII.get(getOpcode(ARMII::SUBri)));
10641069 }
10651070
10661071 // Common case: small offset, fits into instruction.
12691274
12701275 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
12711276 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size);
1272 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1277 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STR), 1, STI);
12731278
12741279 // Darwin ABI requires FP to point to the stack slot that contains the
12751280 // previous FP.
12761281 if (STI.isTargetDarwin() || hasFP(MF)) {
12771282 MachineInstrBuilder MIB =
1278 BuildMI(MBB, MBBI, dl, TII.get(ARM::ADDri), FramePtr)
1283 BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::ADDri)), FramePtr)
12791284 .addFrameIndex(FramePtrSpillFI).addImm(0);
12801285 AddDefaultCC(AddDefaultPred(MIB));
12811286 }
12841289 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size);
12851290
12861291 // Build the new SUBri to adjust SP for FP callee-save spill area.
1287 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1292 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STR), 2, STI);
12881293 emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize);
12891294
12901295 // Determine starting offsets of spill areas.
12991304 NumBytes = DPRCSOffset;
13001305 if (NumBytes) {
13011306 // Insert it after all the callee-save spills.
1302 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1307 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FSTD), 3, STI);
13031308 emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
13041309 }
13051310
13201325 return false;
13211326 }
13221327
1323 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1324 return ((MI->getOpcode() == ARM::FLDD ||
1325 MI->getOpcode() == ARM::LDR) &&
1328 static bool isCSRestore(MachineInstr *MI,
1329 const ARMBaseInstrInfo &TII,
1330 const unsigned *CSRegs) {
1331 return ((MI->getOpcode() == (int)TII.getOpcode(ARMII::FLDD) ||
1332 MI->getOpcode() == (int)TII.getOpcode(ARMII::LDR)) &&
13261333 MI->getOperand(1).isFI() &&
13271334 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
13281335 }
13311338 emitEpilogue(MachineFunction &MF,
13321339 MachineBasicBlock &MBB) const {
13331340 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1334 assert(MBBI->getOpcode() == ARM::BX_RET &&
1341 assert(MBBI->getOpcode() == (int)getOpcode(ARMII::BX_RET) &&
13351342 "Can only insert epilog into returning blocks");
13361343 DebugLoc dl = MBBI->getDebugLoc();
13371344 MachineFrameInfo *MFI = MF.getFrameInfo();
13481355 if (MBBI != MBB.begin()) {
13491356 do
13501357 --MBBI;
1351 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1352 if (!isCSRestore(MBBI, CSRegs))
1358 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1359 if (!isCSRestore(MBBI, TII, CSRegs))
13531360 ++MBBI;
13541361 }
13551362
13691376 AFI->getDPRCalleeSavedAreaOffset()||
13701377 hasFP(MF)) {
13711378 if (NumBytes)
1372 BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1379 BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::SUBri)), ARM::SP).addReg(FramePtr)
13731380 .addImm(NumBytes)
13741381 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
13751382 else
1376 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
1383 BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::MOVr)), ARM::SP).addReg(FramePtr)
13771384 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
13781385 }
13791386 } else if (NumBytes) {
13811388 }
13821389
13831390 // Move SP to start of integer callee save spill area 2.
1384 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1391 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FLDD), 3, STI);
13851392 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize());
13861393
13871394 // Move SP to start of integer callee save spill area 1.
1388 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1395 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDR), 2, STI);
13891396 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size());
13901397
13911398 // Move SP to SP upon entry to the function.
1392 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1399 movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDR), 1, STI);
13931400 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size());
13941401 }
13951402
5454 // Can be only subclassed.
5555 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
5656
57 // Return the opcode that implements 'Op', or 0 if no opcode
58 unsigned getOpcode(int Op) const;
59
5760 public:
5861 /// getRegisterNumbering - Given the enum value for some register, e.g.
5962 /// ARM::LR, return the number that it corresponds to (e.g. 14).
106109 /// specified immediate.
107110 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
108111 MachineBasicBlock::iterator &MBBI,
109 const TargetInstrInfo *TII, DebugLoc dl,
112 DebugLoc dl,
110113 unsigned DestReg, int Val,
111114 ARMCC::CondCodes Pred = ARMCC::AL,
112115 unsigned PredReg = 0) const;
7272 case ARMII::BR_JTr: return ARM::BR_JTr;
7373 case ARMII::BR_JTm: return ARM::BR_JTm;
7474 case ARMII::BR_JTadd: return ARM::BR_JTadd;
75 case ARMII::BX_RET: return ARM::BX_RET;
7576 case ARMII::FCPYS: return ARM::FCPYS;
7677 case ARMII::FCPYD: return ARM::FCPYD;
7778 case ARMII::FLDD: return ARM::FLDD;
119120 const MachineInstr *Orig) const {
120121 DebugLoc dl = Orig->getDebugLoc();
121122 if (Orig->getOpcode() == ARM::MOVi2pieces) {
122 RI.emitLoadConstPool(MBB, I, this, dl,
123 RI.emitLoadConstPool(MBB, I, dl,
123124 DestReg,
124125 Orig->getOperand(1).getImm(),
125126 (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
10621062 // Control-Flow Instructions
10631063 //
10641064
1065 //let isReturn = 1, isTerminator = 1 in
1066 // def t2BX_RET : T2XI<(outs), (ins), "bx lr", [(ARMretflag)]>;
1067 //
1065 let isReturn = 1, isTerminator = 1 in
1066 def t2BX_RET : T2XI<(outs), (ins), "bx lr", [(ARMretflag)]>;
1067
10681068 // On non-Darwin platforms R9 is callee-saved.
1069 //let isCall = 1,
1070 // Defs = [R0, R1, R2, R3, R12, LR,
1071 // D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1072 //def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops),
1073 // "bl ${func:call}",
1074 // [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
1075 //
1076 //def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops),
1077 // "blx $func",
1078 // [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>;
1079 //}
1069 let isCall = 1,
1070 Defs = [R0, R1, R2, R3, R12, LR,
1071 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1072 def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops),
1073 "bl ${func:call}",
1074 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
1075
1076 def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops),
1077 "blx $func",
1078 [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>;
1079 }
10801080
10811081 // On Darwin R9 is call-clobbered.
1082 //let isCall = 1,
1083 // Defs = [R0, R1, R2, R3, R9, R12, LR,
1084 // D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1085 //def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops),
1086 // "bl ${func:call}",
1087 // [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
1088 //
1089 //def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops),
1090 // "blx $func",
1091 // [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>;
1092 //}
1082 let isCall = 1,
1083 Defs = [R0, R1, R2, R3, R9, R12, LR,
1084 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
1085 def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops),
1086 "bl ${func:call}",
1087 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
1088
1089 def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops),
1090 "blx $func",
1091 [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>;
1092 }
10931093
10941094 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
10951095 let isPredicable = 1 in
1212
1313 #include "ARM.h"
1414 #include "ARMAddressingModes.h"
15 #include "ARMBaseInstrInfo.h"
1516 #include "ARMInstrInfo.h"
1617 #include "ARMMachineFunctionInfo.h"
1718 #include "ARMRegisterInfo.h"
4141 case ARMII::BR_JTr: return ARM::tBR_JTr;
4242 case ARMII::BR_JTm: return 0;
4343 case ARMII::BR_JTadd: return 0;
44 case ARMII::BX_RET: return ARM::tBX_RET;
4445 case ARMII::FCPYS: return 0;
4546 case ARMII::FCPYD: return 0;
4647 case ARMII::FLDD: return 0;
1212
1313 #include "ARM.h"
1414 #include "ARMAddressingModes.h"
15 #include "ARMBaseInstrInfo.h"
1516 #include "ARMMachineFunctionInfo.h"
1617 #include "ARMSubtarget.h"
1718 #include "Thumb1InstrInfo.h"
4647 /// specified immediate.
4748 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
4849 MachineBasicBlock::iterator &MBBI,
49 const TargetInstrInfo *TII, DebugLoc dl,
50 DebugLoc dl,
5051 unsigned DestReg, int Val,
5152 ARMCC::CondCodes Pred,
5253 unsigned PredReg) const {
5556 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
5657 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
5758
58 BuildMI(MBB, MBBI, dl, TII->get(ARM::tLDRcp), DestReg)
59 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp), DestReg)
5960 .addConstantPoolIndex(Idx);
6061 }
6162
130131 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
131132 .addReg(LdReg, RegState::Kill);
132133 } else
133 MRI.emitLoadConstPool(MBB, MBBI, &TII, dl, LdReg, NumBytes);
134 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, NumBytes);
134135
135136 // Emit add / sub.
136137 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
504505 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
505506 Offset, false, TII, *this, dl);
506507 else {
507 emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
508 emitLoadConstPool(MBB, II, dl, TmpReg, Offset);
508509 UseRR = true;
509510 }
510511 } else
542543 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
543544 Offset, false, TII, *this, dl);
544545 else {
545 emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
546 emitLoadConstPool(MBB, II, dl, TmpReg, Offset);
546547 UseRR = true;
547548 }
548549 } else
3030 /// specified immediate.
3131 void emitLoadConstPool(MachineBasicBlock &MBB,
3232 MachineBasicBlock::iterator &MBBI,
33 const TargetInstrInfo *TII, DebugLoc dl,
33 DebugLoc dl,
3434 unsigned DestReg, int Val,
3535 ARMCC::CondCodes Pred = ARMCC::AL,
3636 unsigned PredReg = 0) const;
4242 case ARMII::BR_JTr: return ARM::t2BR_JTr;
4343 case ARMII::BR_JTm: return ARM::t2BR_JTm;
4444 case ARMII::BR_JTadd: return ARM::t2BR_JTadd;
45 case ARMII::BX_RET: return ARM::t2BX_RET;
4546 case ARMII::FCPYS: return ARM::FCPYS;
4647 case ARMII::FCPYD: return ARM::FCPYD;
4748 case ARMII::FLDD: return ARM::FLDD;
1212
1313 #include "ARM.h"
1414 #include "ARMAddressingModes.h"
15 #include "ARMBaseInstrInfo.h"
1516 #include "ARMMachineFunctionInfo.h"
1617 #include "ARMSubtarget.h"
1718 #include "Thumb2InstrInfo.h"
4647 /// specified immediate.
4748 void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
4849 MachineBasicBlock::iterator &MBBI,
49 const TargetInstrInfo *TII, DebugLoc dl,
50 DebugLoc dl,
5051 unsigned DestReg, int Val,
5152 ARMCC::CondCodes Pred,
5253 unsigned PredReg) const {
5556 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
5657 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
5758
58 BuildMI(MBB, MBBI, dl, TII->get(ARM::tLDRcp), DestReg)
59 .addConstantPoolIndex(Idx);
59 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci), DestReg)
60 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
6061 }
6162
6263 const TargetRegisterClass*
130131 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
131132 .addReg(LdReg, RegState::Kill);
132133 } else
133 MRI.emitLoadConstPool(MBB, MBBI, &TII, dl, LdReg, NumBytes);
134 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, NumBytes);
134135
135136 // Emit add / sub.
136137 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
504505 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
505506 Offset, false, TII, *this, dl);
506507 else {
507 emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
508 emitLoadConstPool(MBB, II, dl, TmpReg, Offset);
508509 UseRR = true;
509510 }
510511 } else
542543 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
543544 Offset, false, TII, *this, dl);
544545 else {
545 emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
546 emitLoadConstPool(MBB, II, dl, TmpReg, Offset);
546547 UseRR = true;
547548 }
548549 } else
3030 /// specified immediate.
3131 void emitLoadConstPool(MachineBasicBlock &MBB,
3232 MachineBasicBlock::iterator &MBBI,
33 const TargetInstrInfo *TII, DebugLoc dl,
33 DebugLoc dl,
3434 unsigned DestReg, int Val,
3535 ARMCC::CondCodes Pred = ARMCC::AL,
3636 unsigned PredReg = 0) const;