llvm.org GIT mirror llvm / 772b1aa
[mips] Duplicate the reciprocal instruction definitions for FP32 Add instruction definitions for FP32 mode for recip.d and rsqrt.d. Previously these instructions were only defined when targeting the full 64-bit FPU model but were not guarded properly. Reviewers: nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D38400 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315318 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Dardis 2 years ago
5 changed file(s) with 37 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
168168 def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
169169 II_RECIP_S>,
170170 ROUND_W_FM_MM<0b0, 0b01001000>;
171 def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
172 II_RECIP_D>,
173 ROUND_W_FM_MM<0b1, 0b01001000>;
171 def RECIP_D32_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
172 II_RECIP_D>,
173 ROUND_W_FM_MM<0b1, 0b01001000>, FGR_32 {
174 let BaseOpcode = "RECIP_D32";
175 }
176 let DecoderNamespace = "MicroMipsFP64" in
177 def RECIP_D64_MM : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd,
178 II_RECIP_D>,
179 ROUND_W_FM_MM<0b1, 0b01001000>, FGR_64;
174180 def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,
175181 II_RECIP_S>,
176182 ROUND_W_FM_MM<0b0, 0b00001000>;
177 def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
183 def RSQRT_D32_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
178184 II_RECIP_D>,
179 ROUND_W_FM_MM<0b1, 0b00001000>;
180 }
185 ROUND_W_FM_MM<0b1, 0b00001000>, FGR_32 {
186 let BaseOpcode = "RSQRT_D32";
187 }
188 let DecoderNamespace = "MicroMipsFP64" in
189 def RSQRT_D64_MM : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd,
190 II_RECIP_D>,
191 ROUND_W_FM_MM<0b1, 0b00001000>, FGR_64;
192 }
181193 let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in {
182194 def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
183195 LW_FM_MM<0x2f>, FGR_32 {
368368 let AdditionalPredicates = [NotInMicroMips] in {
369369 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
370370 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
371 def RECIP_D : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, II_RECIP_D>,
372 ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2;
371 def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>,
372 ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 {
373 let BaseOpcode = "RECIP_D32";
374 }
375 let DecoderNamespace = "MipsFP64" in
376 def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd,
377 II_RECIP_D>, ABSS_FM<0b010101, 0x11>,
378 INSN_MIPS4_32R2, FGR_64;
373379 def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,
374380 ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;
375 def RSQRT_D : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, II_RSQRT_D>,
376 ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2;
381 def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>,
382 ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 {
383 let BaseOpcode = "RSQRT_D32";
384 }
385 let DecoderNamespace = "MipsFP64" in
386 def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd,
387 II_RSQRT_D>, ABSS_FM<0b010110, 0x11>,
388 INSN_MIPS4_32R2, FGR_64;
377389 }
378390 let DecoderNamespace = "MipsFP64" in {
379391 let AdditionalPredicates = [NotInMicroMips] in {
196196 # CHECK-NEXT: .set mips32r2
197197 # CHECK-NEXT: rdhwr $sp, $11
198198 # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
199 recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
199 recip.d $f14,$f6 # CHECK: recip.d $f14, $f6 # encoding: [0x46,0x20,0x33,0x95]
200200 recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
201201 rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
202202 rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
196196 # CHECK-NEXT: .set mips32r2
197197 # CHECK-NEXT: rdhwr $sp, $11
198198 # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
199 recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
199 recip.d $f14,$f6 # CHECK: recip.d $f14, $f6 # encoding: [0x46,0x20,0x33,0x95]
200200 recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
201201 rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
202202 rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
197197 # CHECK-NEXT: .set mips32r2
198198 # CHECK-NEXT: rdhwr $sp, $11
199199 # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
200 recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
200 recip.d $f14,$f6 # CHECK: recip.d $f14, $f6 # encoding: [0x46,0x20,0x33,0x95]
201201 recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
202202 rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
203203 rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]