llvm.org GIT mirror llvm / 771a901
[TargetLowering] fix SETCC SETLT folding with FP types The bug was introduced with: https://reviews.llvm.org/rL294863 ...and manifests as a selection failure in x86, but that's actually another bug. This fix prevents wrong codegen with -0.0, but in the more common case when we have NSZ and NNAN (-ffast-math), we should still be able to fold this setcc/compare. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294924 91177308-0d34-0410-b5e6-96231b3b80d8 Sanjay Patel 3 years ago
2 changed file(s) with 37 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
750750 KnownOne &= KnownOne2;
751751 KnownZero &= KnownZero2;
752752 break;
753 case ISD::SETCC:
753 case ISD::SETCC: {
754 SDValue Op0 = Op.getOperand(0);
755 SDValue Op1 = Op.getOperand(1);
756 ISD::CondCode CC = cast(Op.getOperand(2))->get();
754757 // If (1) we only need the sign-bit, (2) the setcc operands are the same
755758 // width as the setcc result, and (3) the result of a setcc conforms to 0 or
756759 // -1, we may be able to bypass the setcc.
757 if (NewMask.isSignBit() &&
758 Op.getOperand(0).getScalarValueSizeInBits() == BitWidth &&
760 if (NewMask.isSignBit() && Op0.getScalarValueSizeInBits() == BitWidth &&
759761 getBooleanContents(Op.getValueType()) ==
760762 BooleanContent::ZeroOrNegativeOneBooleanContent) {
761 ISD::CondCode CC = cast(Op.getOperand(2))->get();
762 // If we're testing if X < 0, then this compare isn't needed - just use X!
763 if (CC == ISD::SETLT &&
764 (isNullConstant(Op.getOperand(1)) ||
765 ISD::isBuildVectorAllZeros(Op.getOperand(1).getNode())))
766 return TLO.CombineTo(Op, Op.getOperand(0));
763 // If we're testing X < 0, then this compare isn't needed - just use X!
764 // FIXME: We're limiting to integer types here, but this should also work
765 // if we don't care about FP signed-zero. The use of SETLT with FP means
766 // that we don't care about NaNs.
767 if (CC == ISD::SETLT && Op1.getValueType().isInteger() &&
768 (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode())))
769 return TLO.CombineTo(Op, Op0);
767770
768771 // TODO: Should we check for other forms of sign-bit comparisons?
769772 // Examples: X <= -1, X >= 0
770773 }
771774 break;
775 }
772776 case ISD::SHL:
773777 if (ConstantSDNode *SA = dyn_cast(Op.getOperand(1))) {
774778 unsigned ShAmt = SA->getZExtValue();
316316 ret <8 x double> %z
317317 }
318318
319 ; If we have a floating-point compare:
320 ; (1) Don't die.
321 ; (2) FIXME: If we don't care about signed-zero (and NaN?), the compare should still get folded.
322
323 define <4 x float> @signbit_sel_v4f32_fcmp(<4 x float> %x, <4 x float> %y, <4 x float> %mask) #0 {
324 ; AVX12F-LABEL: signbit_sel_v4f32_fcmp:
325 ; AVX12F: # BB#0:
326 ; AVX12F-NEXT: vxorps %xmm2, %xmm2, %xmm2
327 ; AVX12F-NEXT: vcmpltps %xmm2, %xmm0, %xmm2
328 ; AVX12F-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
329 ; AVX12F-NEXT: retq
330 ;
331 ; AVX512VL-LABEL: signbit_sel_v4f32_fcmp:
332 ; AVX512VL: # BB#0:
333 ; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
334 ; AVX512VL-NEXT: vcmpltps %xmm2, %xmm0, %k1
335 ; AVX512VL-NEXT: vblendmps %xmm0, %xmm1, %xmm0 {%k1}
336 ; AVX512VL-NEXT: retq
337 %cmp = fcmp olt <4 x float> %x, zeroinitializer
338 %sel = select <4 x i1> %cmp, <4 x float> %x, <4 x float> %y
339 ret <4 x float> %sel
340 }
341
342 attributes #0 = { "no-nans-fp-math"="true" }