llvm.org GIT mirror llvm / 770bcc7
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
20 changed file(s) with 65 addition(s) and 74 deletion(s). Raw diff Collapse all Expand all
430430 /// instruction that defines the specified register class.
431431 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
432432 return true;
433 }
434
435 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
436 /// values.
437 virtual const TargetRegisterClass *getPointerRegClass() const {
438 assert(0 && "Target didn't implement getPointerRegClass!");
439 abort();
440 return 0; // Must return a value in order to compile with VS 2005
441433 }
442434
443435 /// GetInstSize - Returns the size of the specified Instruction.
421421 return i ? RegClassBegin[i - 1] : NULL;
422422 }
423423
424 //===--------------------------------------------------------------------===//
425 // Interfaces used by the register allocator and stack frame
426 // manipulation passes to move data around between registers,
427 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
428 //
424 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
425 /// values.
426 virtual const TargetRegisterClass *getPointerRegClass() const {
427 assert(0 && "Target didn't implement getPointerRegClass!");
428 abort();
429 return 0; // Must return a value in order to compile with VS 2005
430 }
429431
430432 /// getCrossCopyRegClass - Returns a legal register class to copy a register
431433 /// in the specified class to or from. Returns NULL if it is possible to copy
477479 ///
478480 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
479481 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
480
481482
482483 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
483484 /// code insertion to eliminate call frame setup and destroy pseudo
236236 /// instruction of the specified TargetInstrDesc.
237237 static const TargetRegisterClass*
238238 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
239 const TargetInstrInfo *TII, const TargetInstrDesc &II,
240 unsigned Op) {
239 const TargetInstrDesc &II, unsigned Op) {
241240 if (Op >= II.getNumOperands())
242241 return NULL;
243242 if (II.OpInfo[Op].isLookupPtrRegClass())
244 return TII->getPointerRegClass();
243 return TRI->getPointerRegClass();
245244 return TRI->getRegClass(II.OpInfo[Op].RegClass);
246245 }
247246
489488 unsigned Reg = MO.getReg();
490489 if (Reg == 0) continue;
491490 const TargetRegisterClass *NewRC =
492 getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
491 getInstrOperandRegClass(TRI, MI->getDesc(), i);
493492
494493 // If this instruction has a use of AntiDepReg, breaking it
495494 // is invalid.
624623 if (!MO.isUse()) continue;
625624
626625 const TargetRegisterClass *NewRC =
627 getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
626 getInstrOperandRegClass(TRI, MI->getDesc(), i);
628627
629628 // For now, only allow the register to be changed if its register
630629 // class is consistent across all uses.
3131 /// instruction of the specified TargetInstrDesc.
3232 static const TargetRegisterClass*
3333 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
34 const TargetInstrInfo *TII, const TargetInstrDesc &II,
35 unsigned Op) {
34 const TargetInstrDesc &II, unsigned Op) {
3635 if (Op >= II.getNumOperands()) {
3736 assert(II.isVariadic() && "Invalid operand # of instruction");
3837 return NULL;
3938 }
4039 if (II.OpInfo[Op].isLookupPtrRegClass())
41 return TII->getPointerRegClass();
40 return TRI->getPointerRegClass();
4241 return TRI->getRegClass(II.OpInfo[Op].RegClass);
4342 }
4443
9089 if (User->isMachineOpcode()) {
9190 const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
9291 const TargetRegisterClass *RC =
93 getInstrOperandRegClass(TRI,TII,II,i+II.getNumDefs());
92 getInstrOperandRegClass(TRI, II, i+II.getNumDefs());
9493 if (!UseRC)
9594 UseRC = RC;
9695 else if (RC)
189188 // Create the result registers for this node and add the result regs to
190189 // the machine instruction.
191190 if (VRBase == 0) {
192 const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i);
191 const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i);
193192 assert(RC && "Isn't a register operand!");
194193 VRBase = MRI.createVirtualRegister(RC);
195194 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
257256 // There may be no register class for this operand if it is a variadic
258257 // argument (RC will be NULL in this case). In this case, we just assume
259258 // the regclass is ok.
260 const TargetRegisterClass *RC =
261 getInstrOperandRegClass(TRI, TII, *II, IIOpNum);
259 const TargetRegisterClass *RC= getInstrOperandRegClass(TRI, *II, IIOpNum);
262260 assert((RC || II->isVariadic()) && "Expected reg class info!");
263261 const TargetRegisterClass *VRC = MRI.getRegClass(VReg);
264262 if (RC && VRC != RC) {
326324 // an FP vreg on x86.
327325 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
328326 if (II && !II->isVariadic()) {
329 assert(getInstrOperandRegClass(TRI, TII, *II, IIOpNum) &&
327 assert(getInstrOperandRegClass(TRI, *II, IIOpNum) &&
330328 "Don't have operand info for this instruction!");
331329 }
332330 }
4242 RI(*this, STI) {
4343 }
4444
45 const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
46 return &ARM::GPRRegClass;
47 }
4845
4946 /// Return true if the instruction is a register to register move and
5047 /// leave the source and dest operands in the passed parameters.
150150 ///
151151 virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
152152
153 /// getPointerRegClass - Return the register class to use to hold pointers.
154 /// This is used for addressing modes.
155 virtual const TargetRegisterClass *getPointerRegClass() const;
156
157153 /// Return true if the instruction is a register to register move and return
158154 /// the source and dest operands and their sub-register indices by reference.
159155 virtual bool isMoveInstr(const MachineInstr &MI,
188188 else
189189 BuildMI(MBB, MBBI, TII->get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx)
190190 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
191 }
192
193 const TargetRegisterClass *ARMRegisterInfo::getPointerRegClass() const {
194 return &ARM::GPRRegClass;
191195 }
192196
193197 /// isLowRegister - Returns true if the register is low register r0-r7.
4747 /// if the register is a single precision VFP register.
4848 static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
4949
50 /// getPointerRegClass - Return the register class to use to hold pointers.
51 /// This is used for addressing modes.
52 const TargetRegisterClass *getPointerRegClass() const;
53
5054 /// Code Generation virtual methods...
5155 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
5256
5151 TM(tm),
5252 RI(*TM.getSubtargetImpl(), *this)
5353 { /* NOP */ }
54
55 /// getPointerRegClass - Return the register class to use to hold pointers.
56 /// This is used for addressing modes.
57 const TargetRegisterClass *
58 SPUInstrInfo::getPointerRegClass() const
59 {
60 return &SPU::R32CRegClass;
61 }
6254
6355 bool
6456 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
4343 /// always be able to get register info as well (through this method).
4444 ///
4545 virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
46
47 /// getPointerRegClass - Return the register class to use to hold pointers.
48 /// This is used for addressing modes.
49 virtual const TargetRegisterClass *getPointerRegClass() const;
5046
5147 /// Return true if the instruction is a register to register move and return
5248 /// the source and dest operands and their sub-register indices by reference.
215215 return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
216216 }
217217
218 /// getPointerRegClass - Return the register class to use to hold pointers.
219 /// This is used for addressing modes.
220 const TargetRegisterClass * SPURegisterInfo::getPointerRegClass() const
221 {
222 return &SPU::R32CRegClass;
223 }
224
218225 const unsigned *
219226 SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
220227 {
3939 e.g. SPU::R14 -> 14.
4040 */
4141 static unsigned getRegisterNumbering(unsigned RegEnum);
42
43 /// getPointerRegClass - Return the register class to use to hold pointers.
44 /// This is used for addressing modes.
45 virtual const TargetRegisterClass *getPointerRegClass() const;
4246
4347 //! Return the array of callee-saved registers
4448 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
2828 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
2929 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
3030 RI(*TM.getSubtargetImpl(), *this) {}
31
32 /// getPointerRegClass - Return the register class to use to hold pointers.
33 /// This is used for addressing modes.
34 const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
35 if (TM.getSubtargetImpl()->isPPC64())
36 return &PPC::G8RCRegClass;
37 else
38 return &PPC::GPRCRegClass;
39 }
40
4131
4232 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
4333 unsigned& sourceReg,
8181 ///
8282 virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; }
8383
84 /// getPointerRegClass - Return the register class to use to hold pointers.
85 /// This is used for addressing modes.
86 virtual const TargetRegisterClass *getPointerRegClass() const;
87
8884 /// Return true if the instruction is a register to register move and return
8985 /// the source and dest operands and their sub-register indices by reference.
9086 virtual bool isMoveInstr(const MachineInstr &MI,
134134 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
135135 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
136136 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
137 }
138
139 /// getPointerRegClass - Return the register class to use to hold pointers.
140 /// This is used for addressing modes.
141 const TargetRegisterClass *PPCRegisterInfo::getPointerRegClass() const {
142 if (Subtarget.isPPC64())
143 return &PPC::G8RCRegClass;
144 else
145 return &PPC::GPRCRegClass;
137146 }
138147
139148 const unsigned*
3333 /// getRegisterNumbering - Given the enum value for some register, e.g.
3434 /// PPC::F14, return the number that it corresponds to (e.g. 14).
3535 static unsigned getRegisterNumbering(unsigned RegEnum);
36
37 /// getPointerRegClass - Return the register class to use to hold pointers.
38 /// This is used for addressing modes.
39 virtual const TargetRegisterClass *getPointerRegClass() const;
3640
3741 /// Code Generation virtual methods...
3842 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
22692269 const TargetInstrDesc &TID = get(Opc);
22702270 const TargetOperandInfo &TOI = TID.OpInfo[Index];
22712271 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2272 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2272 ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
22732273 SmallVector AddrOps;
22742274 SmallVector BeforeOps;
22752275 SmallVector AfterOps;
23442344 if (UnfoldStore) {
23452345 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
23462346 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
2347 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2347 ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
23482348 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
23492349 }
23502350
23682368 const TargetInstrDesc &TID = get(Opc);
23692369 const TargetOperandInfo &TOI = TID.OpInfo[Index];
23702370 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2371 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2371 ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
23722372 std::vector AddrOps;
23732373 std::vector BeforeOps;
23742374 std::vector AfterOps;
24052405 if (TID.getNumDefs() > 0) {
24062406 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
24072407 DstRC = DstTOI.isLookupPtrRegClass()
2408 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2408 ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
24092409 VTs.push_back(*DstRC->vt_begin());
24102410 }
24112411 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
24872487 // allow any loads of these registers before FpGet_ST0_80.
24882488 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
24892489 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2490 }
2491
2492 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
2493 const X86Subtarget *Subtarget = &TM.getSubtarget();
2494 if (Subtarget->is64Bit())
2495 return &X86::GR64RegClass;
2496 else
2497 return &X86::GR32RegClass;
24982490 }
24992491
25002492 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
409409 /// instruction that defines the specified register class.
410410 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
411411
412 const TargetRegisterClass *getPointerRegClass() const;
413
414412 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
415413 // specified machine instruction.
416414 //
148148 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
149149 return 0;
150150 }
151 }
152
153 const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
154 const X86Subtarget *Subtarget = &TM.getSubtarget();
155 if (Subtarget->is64Bit())
156 return &X86::GR64RegClass;
157 else
158 return &X86::GR32RegClass;
151159 }
152160
153161 const TargetRegisterClass *
9292 /// Code Generation virtual methods...
9393 ///
9494
95 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
96 /// values.
97 const TargetRegisterClass *getPointerRegClass() const;
98
9599 /// getCrossCopyRegClass - Returns a legal register class to copy a register
96100 /// in the specified class to or from. Returns NULL if it is possible to copy
97101 /// between a two registers of the specified class.