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Revert "Revert r347596 "Support for inserting profile-directed cache prefetches"" Summary: This reverts commit d8517b96dfbd42e6a8db33c50d1fa1e58e63fbb9. Fix: correct the use of DenseMap. Reviewers: davidxl, hans, wmi Reviewed By: wmi Subscribers: mgorny, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D55088 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347938 91177308-0d34-0410-b5e6-96231b3b80d8 Mircea Trofin 1 year, 9 months ago
16 changed file(s) with 691 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
2929 X86CmovConversion.cpp
3030 X86CondBrFolding.cpp
3131 X86DomainReassignment.cpp
32 X86DiscriminateMemOps.cpp
3233 X86ExpandPseudo.cpp
3334 X86FastISel.cpp
3435 X86FixupBWInsts.cpp
4344 X86ISelLowering.cpp
4445 X86IndirectBranchTracking.cpp
4546 X86InterleavedAccess.cpp
47 X86InsertPrefetch.cpp
4648 X86InstrFMA3Info.cpp
4749 X86InstrFoldTables.cpp
4850 X86InstrInfo.cpp
3030 type = Library
3131 name = X86CodeGen
3232 parent = X86
33 required_libraries = Analysis AsmPrinter CodeGen Core MC SelectionDAG Support Target X86AsmPrinter X86Desc X86Info X86Utils GlobalISel
33 required_libraries = Analysis AsmPrinter CodeGen Core MC SelectionDAG Support Target X86AsmPrinter X86Desc X86Info X86Utils GlobalISel ProfileData
3434 add_to_library_groups = X86
121121 /// This pass creates the thunks for the retpoline feature.
122122 FunctionPass *createX86RetpolineThunksPass();
123123
124 /// This pass ensures instructions featuring a memory operand
125 /// have distinctive (with respect to eachother)
126 FunctionPass *createX86DiscriminateMemOpsPass();
127
128 /// This pass applies profiling information to insert cache prefetches.
129 FunctionPass *createX86InsertPrefetchPass();
130
124131 InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
125132 X86Subtarget &,
126133 X86RegisterBankInfo &);
0 //===- X86DiscriminateMemOps.cpp - Unique IDs for Mem Ops -----------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This pass aids profile-driven cache prefetch insertion by ensuring all
10 /// instructions that have a memory operand are distinguishible from each other.
11 ///
12 //===----------------------------------------------------------------------===//
13
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/IR/DebugInfoMetadata.h"
21 #include "llvm/ProfileData/SampleProf.h"
22 #include "llvm/ProfileData/SampleProfReader.h"
23 #include "llvm/Transforms/IPO/SampleProfile.h"
24 using namespace llvm;
25
26 namespace {
27
28 using Location = std::pair;
29
30 Location diToLocation(const DILocation *Loc) {
31 return std::make_pair(Loc->getFilename(), Loc->getLine());
32 }
33
34 /// Ensure each instruction having a memory operand has a distinct
35 /// Discriminator> pair.
36 void updateDebugInfo(MachineInstr *MI, const DILocation *Loc) {
37 DebugLoc DL(Loc);
38 MI->setDebugLoc(DL);
39 }
40
41 class X86DiscriminateMemOps : public MachineFunctionPass {
42 bool runOnMachineFunction(MachineFunction &MF) override;
43 StringRef getPassName() const override {
44 return "X86 Discriminate Memory Operands";
45 }
46
47 public:
48 static char ID;
49
50 /// Default construct and initialize the pass.
51 X86DiscriminateMemOps();
52 };
53
54 } // end anonymous namespace
55
56 //===----------------------------------------------------------------------===//
57 // Implementation
58 //===----------------------------------------------------------------------===//
59
60 char X86DiscriminateMemOps::ID = 0;
61
62 /// Default construct and initialize the pass.
63 X86DiscriminateMemOps::X86DiscriminateMemOps() : MachineFunctionPass(ID) {}
64
65 bool X86DiscriminateMemOps::runOnMachineFunction(MachineFunction &MF) {
66 DISubprogram *FDI = MF.getFunction().getSubprogram();
67 if (!FDI || !FDI->getUnit()->getDebugInfoForProfiling())
68 return false;
69
70 // Have a default DILocation, if we find instructions with memops that don't
71 // have any debug info.
72 const DILocation *ReferenceDI =
73 DILocation::get(FDI->getContext(), FDI->getLine(), 0, FDI);
74
75 DenseMap MemOpDiscriminators;
76 MemOpDiscriminators[diToLocation(ReferenceDI)] = 0;
77
78 // Figure out the largest discriminator issued for each Location. When we
79 // issue new discriminators, we can thus avoid issuing discriminators
80 // belonging to instructions that don't have memops. This isn't a requirement
81 // for the goals of this pass, however, it avoids unnecessary ambiguity.
82 for (auto &MBB : MF) {
83 for (auto &MI : MBB) {
84 const auto &DI = MI.getDebugLoc();
85 if (!DI)
86 continue;
87 Location Loc = diToLocation(DI);
88 MemOpDiscriminators[Loc] =
89 std::max(MemOpDiscriminators[Loc], DI->getBaseDiscriminator());
90 }
91 }
92
93 // Keep track of the discriminators seen at each Location. If an instruction's
94 // DebugInfo has a Location and discriminator we've already seen, replace its
95 // discriminator with a new one, to guarantee uniqueness.
96 DenseMap> Seen;
97
98 bool Changed = false;
99 for (auto &MBB : MF) {
100 for (auto &MI : MBB) {
101 if (X86II::getMemoryOperandNo(MI.getDesc().TSFlags) < 0)
102 continue;
103 const DILocation *DI = MI.getDebugLoc();
104 if (!DI) {
105 DI = ReferenceDI;
106 }
107 DenseSet &Set = Seen[diToLocation(DI)];
108 const std::pair::iterator, bool> TryInsert =
109 Set.insert(DI->getBaseDiscriminator());
110 if (!TryInsert.second) {
111 DI = DI->setBaseDiscriminator(++MemOpDiscriminators[diToLocation(DI)]);
112 updateDebugInfo(&MI, DI);
113 Changed = true;
114 const std::pair::iterator, bool> MustInsert =
115 Set.insert(DI->getBaseDiscriminator());
116 assert(MustInsert.second);
117 }
118
119 // Bump the reference DI to avoid cramming discriminators on line 0.
120 // FIXME(mtrofin): pin ReferenceDI on blocks or first instruction with DI
121 // in a block. It's more consistent than just relying on the last memop
122 // instruction we happened to see.
123 ReferenceDI = DI;
124 }
125 }
126 return Changed;
127 }
128
129 FunctionPass *llvm::createX86DiscriminateMemOpsPass() {
130 return new X86DiscriminateMemOps();
131 }
0 //===------- X86InsertPrefetch.cpp - Insert cache prefetch hints ----------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass applies cache prefetch instructions based on a profile. The pass
10 // assumes DiscriminateMemOps ran immediately before, to ensure debug info
11 // matches the one used at profile generation time. The profile is encoded in
12 // afdo format (text or binary). It contains prefetch hints recommendations.
13 // Each recommendation is made in terms of debug info locations, a type (i.e.
14 // nta, t{0|1|2}) and a delta. The debug info identifies an instruction with a
15 // memory operand (see X86DiscriminateMemOps). The prefetch will be made for
16 // a location at that memory operand + the delta specified in the
17 // recommendation.
18 //
19 //===----------------------------------------------------------------------===//
20
21 #include "X86.h"
22 #include "X86InstrBuilder.h"
23 #include "X86InstrInfo.h"
24 #include "X86MachineFunctionInfo.h"
25 #include "X86Subtarget.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/IR/DebugInfoMetadata.h"
28 #include "llvm/ProfileData/SampleProf.h"
29 #include "llvm/ProfileData/SampleProfReader.h"
30 #include "llvm/Transforms/IPO/SampleProfile.h"
31 using namespace llvm;
32 using namespace sampleprof;
33
34 static cl::opt
35 PrefetchHintsFile("prefetch-hints-file",
36 cl::desc("Path to the prefetch hints profile."),
37 cl::Hidden);
38 namespace {
39
40 class X86InsertPrefetch : public MachineFunctionPass {
41 void getAnalysisUsage(AnalysisUsage &AU) const override;
42 bool doInitialization(Module &) override;
43
44 bool runOnMachineFunction(MachineFunction &MF) override;
45 struct PrefetchInfo {
46 unsigned InstructionID;
47 int64_t Delta;
48 };
49 typedef SmallVectorImpl Prefetches;
50 bool findPrefetchInfo(const FunctionSamples *Samples, const MachineInstr &MI,
51 Prefetches &prefetches) const;
52
53 public:
54 static char ID;
55 X86InsertPrefetch(const std::string &PrefetchHintsFilename);
56 StringRef getPassName() const override {
57 return "X86 Insert Cache Prefetches";
58 }
59
60 private:
61 std::string Filename;
62 std::unique_ptr Reader;
63 };
64
65 using PrefetchHints = SampleRecord::CallTargetMap;
66
67 // Return any prefetching hints for the specified MachineInstruction. The hints
68 // are returned as pairs (name, delta).
69 ErrorOr getPrefetchHints(const FunctionSamples *TopSamples,
70 const MachineInstr &MI) {
71 if (const auto &Loc = MI.getDebugLoc())
72 if (const auto *Samples = TopSamples->findFunctionSamples(Loc))
73 return Samples->findCallTargetMapAt(FunctionSamples::getOffset(Loc),
74 Loc->getBaseDiscriminator());
75 return std::error_code();
76 }
77
78 // The prefetch instruction can't take memory operands involving vector
79 // registers.
80 bool IsMemOpCompatibleWithPrefetch(const MachineInstr &MI, int Op) {
81 unsigned BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg();
82 unsigned IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg();
83 return (BaseReg == 0 ||
84 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) ||
85 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg)) &&
86 (IndexReg == 0 ||
87 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
88 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg));
89 }
90
91 } // end anonymous namespace
92
93 //===----------------------------------------------------------------------===//
94 // Implementation
95 //===----------------------------------------------------------------------===//
96
97 char X86InsertPrefetch::ID = 0;
98
99 X86InsertPrefetch::X86InsertPrefetch(const std::string &PrefetchHintsFilename)
100 : MachineFunctionPass(ID), Filename(PrefetchHintsFilename) {}
101
102 /// Return true if the provided MachineInstruction has cache prefetch hints. In
103 /// that case, the prefetch hints are stored, in order, in the Prefetches
104 /// vector.
105 bool X86InsertPrefetch::findPrefetchInfo(const FunctionSamples *TopSamples,
106 const MachineInstr &MI,
107 Prefetches &Prefetches) const {
108 assert(Prefetches.empty() &&
109 "Expected caller passed empty PrefetchInfo vector.");
110 static const std::pair HintTypes[] = {
111 {"_nta_", X86::PREFETCHNTA},
112 {"_t0_", X86::PREFETCHT0},
113 {"_t1_", X86::PREFETCHT1},
114 {"_t2_", X86::PREFETCHT2},
115 };
116 static const char *SerializedPrefetchPrefix = "__prefetch";
117
118 const ErrorOr T = getPrefetchHints(TopSamples, MI);
119 if (!T)
120 return false;
121 int16_t max_index = -1;
122 // Convert serialized prefetch hints into PrefetchInfo objects, and populate
123 // the Prefetches vector.
124 for (const auto &S_V : *T) {
125 StringRef Name = S_V.getKey();
126 if (Name.consume_front(SerializedPrefetchPrefix)) {
127 int64_t D = static_cast(S_V.second);
128 unsigned IID = 0;
129 for (const auto &HintType : HintTypes) {
130 if (Name.startswith(HintType.first)) {
131 Name = Name.drop_front(HintType.first.size());
132 IID = HintType.second;
133 break;
134 }
135 }
136 if (IID == 0)
137 return false;
138 uint8_t index = 0;
139 Name.consumeInteger(10, index);
140
141 if (index >= Prefetches.size())
142 Prefetches.resize(index + 1);
143 Prefetches[index] = {IID, D};
144 max_index = std::max(max_index, static_cast(index));
145 }
146 }
147 assert(max_index + 1 >= 0 &&
148 "Possible overflow: max_index + 1 should be positive.");
149 assert(static_cast(max_index + 1) == Prefetches.size() &&
150 "The number of prefetch hints received should match the number of "
151 "PrefetchInfo objects returned");
152 return !Prefetches.empty();
153 }
154
155 bool X86InsertPrefetch::doInitialization(Module &M) {
156 if (Filename.empty())
157 return false;
158
159 LLVMContext &Ctx = M.getContext();
160 ErrorOr> ReaderOrErr =
161 SampleProfileReader::create(Filename, Ctx);
162 if (std::error_code EC = ReaderOrErr.getError()) {
163 std::string Msg = "Could not open profile: " + EC.message();
164 Ctx.diagnose(DiagnosticInfoSampleProfile(Filename, Msg,
165 DiagnosticSeverity::DS_Warning));
166 return false;
167 }
168 Reader = std::move(ReaderOrErr.get());
169 Reader->read();
170 return true;
171 }
172
173 void X86InsertPrefetch::getAnalysisUsage(AnalysisUsage &AU) const {
174 AU.setPreservesAll();
175 AU.addRequired();
176 }
177
178 bool X86InsertPrefetch::runOnMachineFunction(MachineFunction &MF) {
179 if (!Reader)
180 return false;
181 const FunctionSamples *Samples = Reader->getSamplesFor(MF.getFunction());
182 if (!Samples)
183 return false;
184
185 bool Changed = false;
186
187 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
188 SmallVector Prefetches;
189 for (auto &MBB : MF) {
190 for (auto MI = MBB.instr_begin(); MI != MBB.instr_end();) {
191 auto Current = MI;
192 ++MI;
193
194 int Offset = X86II::getMemoryOperandNo(Current->getDesc().TSFlags);
195 if (Offset < 0)
196 continue;
197 unsigned Bias = X86II::getOperandBias(Current->getDesc());
198 int MemOpOffset = Offset + Bias;
199 // FIXME(mtrofin): ORE message when the recommendation cannot be taken.
200 if (!IsMemOpCompatibleWithPrefetch(*Current, MemOpOffset))
201 continue;
202 Prefetches.clear();
203 if (!findPrefetchInfo(Samples, *Current, Prefetches))
204 continue;
205 assert(!Prefetches.empty() &&
206 "The Prefetches vector should contain at least a value if "
207 "findPrefetchInfo returned true.");
208 for (auto &PrefInfo : Prefetches) {
209 unsigned PFetchInstrID = PrefInfo.InstructionID;
210 int64_t Delta = PrefInfo.Delta;
211 const MCInstrDesc &Desc = TII->get(PFetchInstrID);
212 MachineInstr *PFetch =
213 MF.CreateMachineInstr(Desc, Current->getDebugLoc(), true);
214 MachineInstrBuilder MIB(MF, PFetch);
215
216 assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 &&
217 X86::AddrIndexReg == 2 && X86::AddrDisp == 3 &&
218 X86::AddrSegmentReg == 4 &&
219 "Unexpected change in X86 operand offset order.");
220
221 // This assumes X86::AddBaseReg = 0, {...}ScaleAmt = 1, etc.
222 // FIXME(mtrofin): consider adding a:
223 // MachineInstrBuilder::set(unsigned offset, op).
224 MIB.addReg(Current->getOperand(MemOpOffset + X86::AddrBaseReg).getReg())
225 .addImm(
226 Current->getOperand(MemOpOffset + X86::AddrScaleAmt).getImm())
227 .addReg(
228 Current->getOperand(MemOpOffset + X86::AddrIndexReg).getReg())
229 .addImm(Current->getOperand(MemOpOffset + X86::AddrDisp).getImm() +
230 Delta)
231 .addReg(Current->getOperand(MemOpOffset + X86::AddrSegmentReg)
232 .getReg());
233
234 if (!Current->memoperands_empty()) {
235 MachineMemOperand *CurrentOp = *(Current->memoperands_begin());
236 MIB.addMemOperand(MF.getMachineMemOperand(
237 CurrentOp, CurrentOp->getOffset() + Delta, CurrentOp->getSize()));
238 }
239
240 // Insert before Current. This is because Current may clobber some of
241 // the registers used to describe the input memory operand.
242 MBB.insert(Current, PFetch);
243 Changed = true;
244 }
245 }
246 }
247 return Changed;
248 }
249
250 FunctionPass *llvm::createX86InsertPrefetchPass() {
251 return new X86InsertPrefetch(PrefetchHintsFile);
252 }
496496 addPass(createX86FixupLEAs());
497497 addPass(createX86EvexToVexInsts());
498498 }
499 addPass(createX86DiscriminateMemOpsPass());
500 addPass(createX86InsertPrefetchPass());
499501 }
500502
501503 void X86PassConfig::addPreEmitPass2() {
5757 ; CHECK-NEXT: Shadow Call Stack
5858 ; CHECK-NEXT: X86 Indirect Branch Tracking
5959 ; CHECK-NEXT: X86 vzeroupper inserter
60 ; CHECK-NEXT: X86 Discriminate Memory Operands
61 ; CHECK-NEXT: X86 Insert Cache Prefetches
6062 ; CHECK-NEXT: Contiguously Lay Out Funclets
6163 ; CHECK-NEXT: StackMap Liveness Analysis
6264 ; CHECK-NEXT: Live DEBUG_VALUE analysis
158158 ; CHECK-NEXT: X86 Atom pad short functions
159159 ; CHECK-NEXT: X86 LEA Fixup
160160 ; CHECK-NEXT: Compressing EVEX instrs to VEX encoding when possible
161 ; CHECK-NEXT: X86 Discriminate Memory Operands
162 ; CHECK-NEXT: X86 Insert Cache Prefetches
161163 ; CHECK-NEXT: Contiguously Lay Out Funclets
162164 ; CHECK-NEXT: StackMap Liveness Analysis
163165 ; CHECK-NEXT: Live DEBUG_VALUE analysis
0 ; RUN: llc < %s | FileCheck %s
1 ;
2 ; original source, compiled with -O3 -gmlt -fdebug-info-for-profiling:
3 ; int sum(int* arr, int pos1, int pos2) {
4 ; return arr[pos1] + arr[pos2];
5 ; }
6 ;
7 ; ModuleID = 'test.cc'
8 source_filename = "test.cc"
9 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
10 target triple = "x86_64-unknown-linux-gnu"
11
12 ; Function Attrs: norecurse nounwind readonly uwtable
13 define i32 @sum(i32* %arr, i32 %pos1, i32 %pos2) !dbg !7 {
14 entry:
15 %idxprom = sext i32 %pos1 to i64, !dbg !9
16 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom, !dbg !9
17 %0 = load i32, i32* %arrayidx, align 4, !dbg !9, !tbaa !10
18 %idxprom1 = sext i32 %pos2 to i64, !dbg !14
19 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1, !dbg !14
20 %1 = load i32, i32* %arrayidx2, align 4, !dbg !14, !tbaa !10
21 %add = add nsw i32 %1, %0, !dbg !15
22 ret i32 %add, !dbg !16
23 }
24
25 attributes #0 = { "target-cpu"="x86-64" }
26
27 !llvm.dbg.cu = !{!0}
28 !llvm.module.flags = !{!3, !4, !5}
29 !llvm.ident = !{!6}
30
31 !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly, enums: !2, debugInfoForProfiling: true)
32 !1 = !DIFile(filename: "test.cc", directory: "/tmp")
33 !2 = !{}
34 !3 = !{i32 2, !"Dwarf Version", i32 4}
35 !4 = !{i32 2, !"Debug Info Version", i32 3}
36 !5 = !{i32 1, !"wchar_size", i32 4}
37 !6 = !{!"clang version 7.0.0 (trunk 322155) (llvm/trunk 322159)"}
38 !7 = distinct !DISubprogram(name: "sum", linkageName: "sum", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
39 !8 = !DISubroutineType(types: !2)
40 !9 = !DILocation(line: 2, column: 10, scope: !7)
41 !10 = !{!11, !11, i64 0}
42 !11 = !{!"int", !12, i64 0}
43 !12 = !{!"omnipotent char", !13, i64 0}
44 !13 = !{!"Simple C++ TBAA"}
45 !14 = !DILocation(line: 2, column: 22, scope: !7)
46 !15 = !DILocation(line: 2, column: 20, scope: !7)
47 !16 = !DILocation(line: 2, column: 3, scope: !7)
48
49 ;CHECK-LABEL: sum:
50 ;CHECK: # %bb.0:
51 ;CHECK: movl (%rdi,%rax,4), %eax
52 ;CHECK-NEXT: .loc 1 2 20 discriminator 2 # test.cc:2:20
53 ;CHECK-NEXT: addl (%rdi,%rcx,4), %eax
54 ;CHECK-NEXT: .loc 1 2 3 # test.cc:2:3
0 caller:0:0
1 2:sum:0
2 3: 0 __prefetch_nta_0:23456
3 3.1: 0 __prefetch_nta_0:8764 __prefetch_nta_1:64
0 ; RUN: llc < %s -prefetch-hints-file=%S/insert-prefetch-inline.afdo | FileCheck %s
1 ;
2 ; Verify we can insert prefetch instructions in code belonging to inlined
3 ; functions.
4 ;
5 ; ModuleID = 'test.cc'
6
7 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
8 target triple = "x86_64-unknown-linux-gnu"
9
10 ; Function Attrs: norecurse nounwind readonly uwtable
11 define dso_local i32 @sum(i32* nocapture readonly %arr, i32 %pos1, i32 %pos2) local_unnamed_addr #0 !dbg !7 {
12 entry:
13 %idxprom = sext i32 %pos1 to i64, !dbg !10
14 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom, !dbg !10
15 %0 = load i32, i32* %arrayidx, align 4, !dbg !10, !tbaa !11
16 %idxprom1 = sext i32 %pos2 to i64, !dbg !15
17 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1, !dbg !15
18 %1 = load i32, i32* %arrayidx2, align 4, !dbg !15, !tbaa !11
19 %add = add nsw i32 %1, %0, !dbg !16
20 ret i32 %add, !dbg !17
21 }
22
23 ; "caller" inlines "sum". The associated .afdo file references instructions
24 ; in "caller" that came from "sum"'s inlining.
25 ;
26 ; Function Attrs: norecurse nounwind readonly uwtable
27 define dso_local i32 @caller(i32* nocapture readonly %arr) local_unnamed_addr #0 !dbg !18 {
28 entry:
29 %0 = load i32, i32* %arr, align 4, !dbg !19, !tbaa !11
30 %arrayidx2.i = getelementptr inbounds i32, i32* %arr, i64 2, !dbg !21
31 %1 = load i32, i32* %arrayidx2.i, align 4, !dbg !21, !tbaa !11
32 %add.i = add nsw i32 %1, %0, !dbg !22
33 ret i32 %add.i, !dbg !23
34 }
35
36 attributes #0 = { "target-cpu"="x86-64" }
37
38 !llvm.dbg.cu = !{!0}
39 !llvm.module.flags = !{!3, !4, !5}
40 !llvm.ident = !{!6}
41
42 !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 7.0.0 (trunk 324940) (llvm/trunk 324941)", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly, enums: !2, debugInfoForProfiling: true)
43 !1 = !DIFile(filename: "test.cc", directory: "/tmp")
44 !2 = !{}
45 !3 = !{i32 2, !"Dwarf Version", i32 4}
46 !4 = !{i32 2, !"Debug Info Version", i32 3}
47 !5 = !{i32 1, !"wchar_size", i32 4}
48 !6 = !{!"clang version 7.0.0 (trunk 324940) (llvm/trunk 324941)"}
49 !7 = distinct !DISubprogram(name: "sum", linkageName: "sum", scope: !8, file: !8, line: 3, type: !9, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
50 !8 = !DIFile(filename: "./test.h", directory: "/tmp")
51 !9 = !DISubroutineType(types: !2)
52 !10 = !DILocation(line: 6, column: 10, scope: !7)
53 !11 = !{!12, !12, i64 0}
54 !12 = !{!"int", !13, i64 0}
55 !13 = !{!"omnipotent char", !14, i64 0}
56 !14 = !{!"Simple C++ TBAA"}
57 !15 = !DILocation(line: 6, column: 22, scope: !7)
58 !16 = !DILocation(line: 6, column: 20, scope: !7)
59 !17 = !DILocation(line: 6, column: 3, scope: !7)
60 !18 = distinct !DISubprogram(name: "caller", linkageName: "caller", scope: !1, file: !1, line: 4, type: !9, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
61 !19 = !DILocation(line: 6, column: 10, scope: !7, inlinedAt: !20)
62 !20 = distinct !DILocation(line: 6, column: 10, scope: !18)
63 !21 = !DILocation(line: 6, column: 22, scope: !7, inlinedAt: !20)
64 !22 = !DILocation(line: 6, column: 20, scope: !7, inlinedAt: !20)
65 !23 = !DILocation(line: 6, column: 3, scope: !18)
66
67 ; CHECK-LABEL: caller:
68 ; CHECK-LABEL: # %bb.0:
69 ; CHECK-NEXT: .loc 1 6 22 prologue_end
70 ; CHECK-NEXT: prefetchnta 23464(%rdi)
71 ; CHECK-NEXT: movl 8(%rdi), %eax
72 ; CHECK-NEXT: .loc 1 6 20 is_stmt 0 discriminator 2
73 ; CHECK-NEXT: prefetchnta 8764(%rdi)
74 ; CHECK-NEXT: prefetchnta 64(%rdi)
75 ; CHECK-NEXT: addl (%rdi), %eax
0 main:0:0
1 6: 0 __prefetch_nta_0:42
0 ; RUN: llc < %s -prefetch-hints-file=%S/insert-prefetch-invalid-instr.afdo | FileCheck %s
1 ; ModuleID = 'prefetch.cc'
2 source_filename = "prefetch.cc"
3 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
4 target triple = "x86_64-unknown-linux-gnu"
5
6 ; Function Attrs: norecurse nounwind uwtable
7 define dso_local i32 @main() local_unnamed_addr #0 !dbg !7 {
8 entry:
9 tail call void @llvm.prefetch(i8* inttoptr (i64 291 to i8*), i32 0, i32 0, i32 1), !dbg !9
10 tail call void @llvm.x86.avx512.gatherpf.dpd.512(i8 97, <8 x i32> undef, i8* null, i32 1, i32 2), !dbg !10
11 ret i32 291, !dbg !11
12 }
13
14 ; Function Attrs: inaccessiblemem_or_argmemonly nounwind
15 declare void @llvm.prefetch(i8* nocapture readonly, i32, i32, i32) #1
16
17 ; Function Attrs: argmemonly nounwind
18 declare void @llvm.x86.avx512.gatherpf.dpd.512(i8, <8 x i32>, i8*, i32, i32) #2
19
20 attributes #0 = {"target-cpu"="x86-64" "target-features"="+avx512pf,+sse4.2,+ssse3"}
21 attributes #1 = { inaccessiblemem_or_argmemonly nounwind }
22 attributes #2 = { argmemonly nounwind }
23
24 !llvm.dbg.cu = !{!0}
25 !llvm.module.flags = !{!3, !4, !5}
26 !llvm.ident = !{!6}
27
28 !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly, enums: !2, debugInfoForProfiling: true)
29 !1 = !DIFile(filename: "prefetch.cc", directory: "/tmp")
30 !2 = !{}
31 !3 = !{i32 2, !"Dwarf Version", i32 4}
32 !4 = !{i32 2, !"Debug Info Version", i32 3}
33 !5 = !{i32 1, !"wchar_size", i32 4}
34 !6 = !{!"clang version 7.0.0 (trunk 327078) (llvm/trunk 327086)"}
35 !7 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 8, type: !8, isLocal: false, isDefinition: true, scopeLine: 8, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
36 !8 = !DISubroutineType(types: !2)
37 !9 = !DILocation(line: 12, column: 3, scope: !7)
38 !10 = !DILocation(line: 14, column: 3, scope: !7)
39 !11 = !DILocation(line: 15, column: 3, scope: !7)
40
41 ;CHECK-LABEL: main:
42 ;CHECK: # %bb.0:
43 ;CHECK: prefetchnta 291
44 ;CHECK-NOT: prefetchnta 42(%rax,%ymm0)
45 ;CHECK: vgatherpf1dpd (%rax,%ymm0) {%k1}
0 sum:0:0
1 1: 0 __prefetch_t0_1:0 __prefetch_t2_0:42
2 1.1: 0 __prefetch_t1_0:18446744073709551615
0 sum:0:0
1 1: 0 __prefetch_nta_1:0 __prefetch_nta_0:42
2 1.1: 0 __prefetch_nta_0:18446744073709551615
0 ; RUN: llc < %s -prefetch-hints-file=%S/insert-prefetch.afdo | FileCheck %s
1 ; RUN: llc < %s -prefetch-hints-file=%S/insert-prefetch-other.afdo | FileCheck %s -check-prefix=OTHERS
2 ;
3 ; original source, compiled with -O3 -gmlt -fdebug-info-for-profiling:
4 ; int sum(int* arr, int pos1, int pos2) {
5 ; return arr[pos1] + arr[pos2];
6 ; }
7 ;
8 ; NOTE: debug line numbers were adjusted such that the function would start
9 ; at line 15 (an arbitrary number). The sample profile file format uses
10 ; offsets from the start of the symbol instead of file-relative line numbers.
11 ; The .afdo file reflects that - the instructions are offset '1'.
12 ;
13 ; ModuleID = 'test.cc'
14 source_filename = "test.cc"
15 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
16 target triple = "x86_64-unknown-linux-gnu"
17
18 define i32 @sum(i32* %arr, i32 %pos1, i32 %pos2) !dbg !35 !prof !37 {
19 entry:
20 %idxprom = sext i32 %pos1 to i64, !dbg !38
21 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom, !dbg !38
22 %0 = load i32, i32* %arrayidx, align 4, !dbg !38, !tbaa !39
23 %idxprom1 = sext i32 %pos2 to i64, !dbg !43
24 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1, !dbg !43
25 %1 = load i32, i32* %arrayidx2, align 4, !dbg !43, !tbaa !39
26 %add = add nsw i32 %1, %0, !dbg !44
27 ret i32 %add, !dbg !45
28 }
29
30 attributes #0 = { "target-cpu"="x86-64" }
31
32 !llvm.dbg.cu = !{!0}
33 !llvm.module.flags = !{!3, !4, !5, !6}
34 !llvm.ident = !{!33}
35
36 !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly, enums: !2, debugInfoForProfiling: true)
37 !1 = !DIFile(filename: "test.cc", directory: "/tmp")
38 !2 = !{}
39 !3 = !{i32 2, !"Dwarf Version", i32 4}
40 !4 = !{i32 2, !"Debug Info Version", i32 3}
41 !5 = !{i32 1, !"wchar_size", i32 4}
42 !6 = !{i32 1, !"ProfileSummary", !7}
43 !7 = !{!8, !9, !10, !11, !12, !13, !14, !15}
44 !8 = !{!"ProfileFormat", !"SampleProfile"}
45 !9 = !{!"TotalCount", i64 0}
46 !10 = !{!"MaxCount", i64 0}
47 !11 = !{!"MaxInternalCount", i64 0}
48 !12 = !{!"MaxFunctionCount", i64 0}
49 !13 = !{!"NumCounts", i64 2}
50 !14 = !{!"NumFunctions", i64 1}
51 !15 = !{!"DetailedSummary", !16}
52 !16 = !{!17, !18, !19, !20, !21, !22, !22, !23, !23, !24, !25, !26, !27, !28, !29, !30, !31, !32}
53 !17 = !{i32 10000, i64 0, i32 0}
54 !18 = !{i32 100000, i64 0, i32 0}
55 !19 = !{i32 200000, i64 0, i32 0}
56 !20 = !{i32 300000, i64 0, i32 0}
57 !21 = !{i32 400000, i64 0, i32 0}
58 !22 = !{i32 500000, i64 0, i32 0}
59 !23 = !{i32 600000, i64 0, i32 0}
60 !24 = !{i32 700000, i64 0, i32 0}
61 !25 = !{i32 800000, i64 0, i32 0}
62 !26 = !{i32 900000, i64 0, i32 0}
63 !27 = !{i32 950000, i64 0, i32 0}
64 !28 = !{i32 990000, i64 0, i32 0}
65 !29 = !{i32 999000, i64 0, i32 0}
66 !30 = !{i32 999900, i64 0, i32 0}
67 !31 = !{i32 999990, i64 0, i32 0}
68 !32 = !{i32 999999, i64 0, i32 0}
69 !33 = !{!"clang version 7.0.0 (trunk 322593) (llvm/trunk 322526)"}
70 !35 = distinct !DISubprogram(name: "sum", linkageName: "sum", scope: !1, file: !1, line: 15, type: !36, isLocal: false, isDefinition: true, scopeLine: 15, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
71 !36 = !DISubroutineType(types: !2)
72 !37 = !{!"function_entry_count", i64 -1}
73 !38 = !DILocation(line: 16, column: 10, scope: !35)
74 !39 = !{!40, !40, i64 0}
75 !40 = !{!"int", !41, i64 0}
76 !41 = !{!"omnipotent char", !42, i64 0}
77 !42 = !{!"Simple C++ TBAA"}
78 !43 = !DILocation(line: 16, column: 22, scope: !35)
79 !44 = !DILocation(line: 16, column: 20, scope: !35)
80 !45 = !DILocation(line: 16, column: 3, scope: !35)
81
82 ;CHECK-LABEL: sum:
83 ;CHECK: # %bb.0:
84 ;CHECK: prefetchnta 42(%rdi,%rax,4)
85 ;CHECK-NEXT: prefetchnta (%rdi,%rax,4)
86 ;CHECK-NEXT: movl (%rdi,%rax,4), %eax
87 ;CHECK-NEXT: .loc 1 16 20 discriminator 2 # test.cc:16:20
88 ;CHECK-NEXT: prefetchnta -1(%rdi,%rcx,4)
89 ;CHECK-NEXT: addl (%rdi,%rcx,4), %eax
90 ;CHECK-NEXT: .loc 1 16 3 # test.cc:16:3
91
92 ;OTHERS-LABEL: sum:
93 ;OTHERS: # %bb.0:
94 ;OTHERS: prefetcht2 42(%rdi,%rax,4)
95 ;OTHERS-NEXT: prefetcht0 (%rdi,%rax,4)
96 ;OTHERS-NEXT: movl (%rdi,%rax,4), %eax
97 ;OTHERS-NEXT: .loc 1 16 20 discriminator 2 # test.cc:16:20
98 ;OTHERS-NEXT: prefetcht1 -1(%rdi,%rcx,4)
99 ;OTHERS-NEXT: addl (%rdi,%rcx,4), %eax
100 ;OTHERS-NEXT: .loc 1 16 3 # test.cc:16:3