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[AMDGPU] Add instruction selection for i1 to f16 conversion Summary: This is required for GPUs with 16 bit instructions where f16 is a legal register type and hence int_to_fp i1 to f16 is not lowered by legalizing. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D52018 Change-Id: Ie4c0fd6ced7cf10ad612023c6879724d9ded5851 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342558 91177308-0d34-0410-b5e6-96231b3b80d8 Carl Ritson 1 year, 9 months ago
3 changed file(s) with 48 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
13201320 >;
13211321
13221322 def : GCNPat <
1323 (f16 (sint_to_fp i1:$src)),
1324 (V_CVT_F16_F32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 CONST.FP32_NEG_ONE), $src))
1325 >;
1326
1327 def : GCNPat <
1328 (f16 (uint_to_fp i1:$src)),
1329 (V_CVT_F16_F32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 CONST.FP32_ONE), $src))
1330 >;
1331
1332 def : GCNPat <
13231333 (f32 (sint_to_fp i1:$src)),
13241334 (V_CNDMASK_B32_e64 (i32 0), (i32 CONST.FP32_NEG_ONE), $src)
13251335 >;
9191 ret void
9292 }
9393
94 ; FUNC-LABEL: {{^}}s_sint_to_fp_i1_to_f16:
95 ; GCN-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 1.0, {{v[0-9]+}}
96 ; GCN-DAG: v_cmp_le_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, {{v[0-9]+}}
97 ; GCN: s_xor_b64 [[R_CMP:s\[[0-9]+:[0-9]+\]]], [[CMP1]], [[CMP0]]
98 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1.0, [[R_CMP]]
99 ; GCN-NEXT: v_cvt_f16_f32_e32 [[R_F16:v[0-9]+]], [[RESULT]]
100 ; GCN: buffer_store_short
101 ; GCN: s_endpgm
102 define amdgpu_kernel void @s_sint_to_fp_i1_to_f16(half addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
103 %a = load float, float addrspace(1) * %in0
104 %b = load float, float addrspace(1) * %in1
105 %acmp = fcmp oge float %a, 0.000000e+00
106 %bcmp = fcmp oge float %b, 1.000000e+00
107 %result = xor i1 %acmp, %bcmp
108 %fp = sitofp i1 %result to half
109 store half %fp, half addrspace(1)* %out
110 ret void
111 }
112
94113 ; v2f16 = sitofp v2i64 is in sint_to_fp.i64.ll
9191 ret void
9292 }
9393
94 ; FUNC-LABEL: {{^}}s_uint_to_fp_i1_to_f16:
95 ; GCN-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 1.0, {{v[0-9]+}}
96 ; GCN-DAG: v_cmp_le_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, {{v[0-9]+}}
97 ; GCN: s_xor_b64 [[R_CMP:s\[[0-9]+:[0-9]+\]]], [[CMP1]], [[CMP0]]
98 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[R_CMP]]
99 ; GCN-NEXT: v_cvt_f16_f32_e32 [[R_F16:v[0-9]+]], [[RESULT]]
100 ; GCN: buffer_store_short
101 ; GCN: s_endpgm
102 define amdgpu_kernel void @s_uint_to_fp_i1_to_f16(half addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
103 %a = load float, float addrspace(1) * %in0
104 %b = load float, float addrspace(1) * %in1
105 %acmp = fcmp oge float %a, 0.000000e+00
106 %bcmp = fcmp oge float %b, 1.000000e+00
107 %result = xor i1 %acmp, %bcmp
108 %fp = uitofp i1 %result to half
109 store half %fp, half addrspace(1)* %out
110 ret void
111 }
112
94113 ; f16 = uitofp i64 is in uint_to_fp.i64.ll