llvm.org GIT mirror llvm / 76914be
Clarify rules for reserved regs, fix aarch64 ones. No test case necessary as the problematic condition is checked with the newly introduced assertAllSuperRegsMarked() function. Differential Revision: https://reviews.llvm.org/D26648 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288277 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 4 years ago
6 changed file(s) with 73 addition(s) and 34 deletion(s). Raw diff Collapse all Expand all
485485
486486 /// Returns a bitset indexed by physical register number indicating if a
487487 /// register is a special register that has particular uses and should be
488 /// considered unavailable at all times, e.g. SP, RA. This is
489 /// used by register scavenger to determine what registers are free.
488 /// considered unavailable at all times, e.g. stack pointer, return address.
489 /// A reserved register:
490 /// - is not allocatable
491 /// - is considered always live
492 /// - is ignored by liveness tracking
493 /// It is often necessary to reserve the super registers of a reserved
494 /// register as well, to avoid them getting allocated indirectly. You may use
495 /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
490496 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
491497
492498 /// Returns true if PhysReg is unallocatable and constant throughout the
941947 /// getFrameRegister - This method should return the register used as a base
942948 /// for values allocated in the current stack frame.
943949 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
950
951 /// Mark a register and all its aliases as reserved in the given set.
952 void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const;
953
954 /// Returns true if for every register in the set all super registers are part
955 /// of the set as well.
956 bool checkAllSuperRegsMarked(const BitVector &RegisterSet,
957 ArrayRef Exceptions = ArrayRef()) const;
944958 };
945959
946960
525525 void MachineVerifier::visitMachineFunctionBefore() {
526526 lastIndex = SlotIndex();
527527 regsReserved = MRI->getReservedRegs();
528
529 // A sub-register of a reserved register is also reserved
530 for (int Reg = regsReserved.find_first(); Reg>=0;
531 Reg = regsReserved.find_next(Reg)) {
532 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
533 // FIXME: This should probably be:
534 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
535 regsReserved.set(*SubRegs);
536 }
537 }
538528
539529 markReachable(&MF->front());
540530
3838 }
3939
4040 TargetRegisterInfo::~TargetRegisterInfo() {}
41
42 void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, unsigned Reg)
43 const {
44 for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
45 RegisterSet.set(*AI);
46 }
47
48 bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
49 ArrayRef Exceptions) const {
50 // Check that all super registers of reserved regs are reserved as well.
51 BitVector Checked(getNumRegs());
52 for (int Reg = RegisterSet.find_first(); Reg>=0;
53 Reg = RegisterSet.find_next(Reg)) {
54 if (Checked[Reg])
55 continue;
56 for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
57 if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
58 dbgs() << "Error: Super register " << PrintReg(*SR, this)
59 << " of reserved register " << PrintReg(Reg, this)
60 << " is not reserved.\n";
61 return false;
62 }
63
64 // We transitively check superregs. So we can remember this for later
65 // to avoid compiletime explosion in deep register hierarchies.
66 Checked.set(*SR);
67 }
68 }
69 return true;
70 }
4171
4272 namespace llvm {
4373
117117
118118 // FIXME: avoid re-calculating this every time.
119119 BitVector Reserved(getNumRegs());
120 Reserved.set(AArch64::SP);
121 Reserved.set(AArch64::XZR);
122 Reserved.set(AArch64::WSP);
123 Reserved.set(AArch64::WZR);
120 markSuperRegs(Reserved, AArch64::SP);
121 markSuperRegs(Reserved, AArch64::XZR);
122 markSuperRegs(Reserved, AArch64::WSP);
123 markSuperRegs(Reserved, AArch64::WZR);
124124
125125 if (TFI->hasFP(MF) || TT.isOSDarwin()) {
126 Reserved.set(AArch64::FP);
127 Reserved.set(AArch64::W29);
126 markSuperRegs(Reserved, AArch64::FP);
127 markSuperRegs(Reserved, AArch64::W29);
128128 }
129129
130130 if (MF.getSubtarget().isX18Reserved()) {
131 Reserved.set(AArch64::X18); // Platform register
132 Reserved.set(AArch64::W18);
131 markSuperRegs(Reserved, AArch64::X18); // Platform register
132 markSuperRegs(Reserved, AArch64::W18);
133133 }
134134
135135 if (hasBasePointer(MF)) {
136 Reserved.set(AArch64::X19);
137 Reserved.set(AArch64::W19);
138 }
139
136 markSuperRegs(Reserved, AArch64::X19);
137 markSuperRegs(Reserved, AArch64::W19);
138 }
139
140 assert(checkAllSuperRegsMarked(Reserved));
140141 return Reserved;
141142 }
142143
166166
167167 // FIXME: avoid re-calculating this every time.
168168 BitVector Reserved(getNumRegs());
169 Reserved.set(ARM::SP);
170 Reserved.set(ARM::PC);
171 Reserved.set(ARM::FPSCR);
172 Reserved.set(ARM::APSR_NZCV);
169 markSuperRegs(Reserved, ARM::SP);
170 markSuperRegs(Reserved, ARM::PC);
171 markSuperRegs(Reserved, ARM::FPSCR);
172 markSuperRegs(Reserved, ARM::APSR_NZCV);
173173 if (TFI->hasFP(MF))
174 Reserved.set(getFramePointerReg(STI));
174 markSuperRegs(Reserved, getFramePointerReg(STI));
175175 if (hasBasePointer(MF))
176 Reserved.set(BasePtr);
176 markSuperRegs(Reserved, BasePtr);
177177 // Some targets reserve R9.
178178 if (STI.isR9Reserved())
179 Reserved.set(ARM::R9);
179 markSuperRegs(Reserved, ARM::R9);
180180 // Reserve D16-D31 if the subtarget doesn't support them.
181181 if (!STI.hasVFP3() || STI.hasD16()) {
182182 static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
183 Reserved.set(ARM::D16, ARM::D31 + 1);
183 for (unsigned R = 0; R < 16; ++R)
184 markSuperRegs(Reserved, ARM::D16 + R);
184185 }
185186 const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
186187 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
187188 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
188 if (Reserved.test(*SI)) Reserved.set(*I);
189
189 if (Reserved.test(*SI)) markSuperRegs(Reserved, *I);
190
191 assert(checkAllSuperRegsMarked(Reserved));
190192 return Reserved;
191193 }
192194
557557 }
558558 }
559559
560 assert(checkAllSuperRegsMarked(Reserved,
561 {X86::SIL, X86::DIL, X86::BPL, X86::SPL}));
560562 return Reserved;
561563 }
562564