llvm.org GIT mirror llvm / 765a762
[MCA] Add support for BeginGroup/EndGroup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349354 91177308-0d34-0410-b5e6-96231b3b80d8 Andrea Di Biagio 1 year, 11 months ago
4 changed file(s) with 22 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
333333 bool MayLoad;
334334 bool MayStore;
335335 bool HasSideEffects;
336 bool BeginGroup;
337 bool EndGroup;
336338
337339 // A zero latency instruction doesn't consume any scheduler resources.
338340 bool isZeroLatency() const { return !MaxLatency && Resources.empty(); }
535535 ID->MayLoad = MCDesc.mayLoad();
536536 ID->MayStore = MCDesc.mayStore();
537537 ID->HasSideEffects = MCDesc.hasUnmodeledSideEffects();
538 ID->BeginGroup = SCDesc.BeginGroup;
539 ID->EndGroup = SCDesc.EndGroup;
538540
539541 initializeUsedResources(*ID, SCDesc, STI, ProcResourceMasks);
540542 computeMaxLatency(*ID, MCDesc, SCDesc, STI);
9898 AvailableEntries -= NumMicroOps;
9999 }
100100
101 // Check if this instructions ends the dispatch group.
102 if (Desc.EndGroup)
103 AvailableEntries = 0;
104
101105 // Check if this is an optimizable reg-reg move.
102106 bool IsEliminated = false;
103107 if (IS.isOptimizableMove()) {
163167 unsigned Required = std::min(Desc.NumMicroOps, DispatchWidth);
164168 if (Required > AvailableEntries)
165169 return false;
170
171 if (Desc.BeginGroup && AvailableEntries != DispatchWidth)
172 return false;
173
166174 // The dispatch logic doesn't internally buffer instructions. It only accepts
167175 // instructions that can be successfully moved to the next stage during this
168176 // same cycle.
55
66 # CHECK: Iterations: 100
77 # CHECK-NEXT: Instructions: 200
8 # CHECK-NEXT: Total Cycles: 1003
8 # CHECK-NEXT: Total Cycles: 1004
99 # CHECK-NEXT: Total uOps: 600
1010
1111 # CHECK: Dispatch Width: 6
5050 # CHECK-NEXT: - - - - 0.10 4.90 - - - - - - - lmg %r6, %r15, 48(%r15)
5151
5252 # CHECK: Timeline view:
53 # CHECK-NEXT: 0123456789 012
53 # CHECK-NEXT: 0123456789 0123
5454 # CHECK-NEXT: Index 0123456789 0123456789
5555
56 # CHECK: [0,0] DeER . . . . . . . stmg %r6, %r15, 48(%r15)
57 # CHECK-NEXT: [0,1] DeeeeeeeeeeER . . . . . lmg %r6, %r15, 48(%r15)
58 # CHECK-NEXT: [1,0] .D=========eER . . . . . stmg %r6, %r15, 48(%r15)
59 # CHECK-NEXT: [1,1] .D=========eeeeeeeeeeER . . . lmg %r6, %r15, 48(%r15)
60 # CHECK-NEXT: [2,0] . D==================eER . . . stmg %r6, %r15, 48(%r15)
61 # CHECK-NEXT: [2,1] . D==================eeeeeeeeeeER lmg %r6, %r15, 48(%r15)
56 # CHECK: [0,0] DeER . . . . . . . stmg %r6, %r15, 48(%r15)
57 # CHECK-NEXT: [0,1] .DeeeeeeeeeeER . . . . . lmg %r6, %r15, 48(%r15)
58 # CHECK-NEXT: [1,0] . D=========eER. . . . . stmg %r6, %r15, 48(%r15)
59 # CHECK-NEXT: [1,1] . D========eeeeeeeeeeER . . . lmg %r6, %r15, 48(%r15)
60 # CHECK-NEXT: [2,0] . D=================eER. . . stmg %r6, %r15, 48(%r15)
61 # CHECK-NEXT: [2,1] . D================eeeeeeeeeeER lmg %r6, %r15, 48(%r15)
6262
6363 # CHECK: Average Wait times (based on the timeline view):
6464 # CHECK-NEXT: [0]: Executions
6767 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
6868
6969 # CHECK: [0] [1] [2] [3]
70 # CHECK-NEXT: 0. 3 10.0 0.3 0.0 stmg %r6, %r15, 48(%r15)
71 # CHECK-NEXT: 1. 3 10.0 0.3 0.0 lmg %r6, %r15, 48(%r15)
70 # CHECK-NEXT: 0. 3 9.7 0.3 0.0 stmg %r6, %r15, 48(%r15)
71 # CHECK-NEXT: 1. 3 9.0 0.3 0.0 lmg %r6, %r15, 48(%r15)