llvm.org GIT mirror llvm / 764b29e
Test Operand Arguments Add a test to do list manipulation and pass the result as arguments. This tests the new list element operator resolve code and provides an example of using list manipulation to do instruction pattern substitution. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141102 91177308-0d34-0410-b5e6-96231b3b80d8 David Greene 7 years ago
1 changed file(s) with 120 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 // RUN: tblgen %s | FileCheck %s
1
2 class ValueType {
3 int Size = size;
4 int Value = value;
5 }
6
7 def v2i64 : ValueType<128, 22>; // 2 x i64 vector value
8 def v2f64 : ValueType<128, 28>; // 2 x f64 vector value
9
10 class Intrinsic {
11 string Name = name;
12 }
13
14 class Pattern resultInstrs> {
15 dag PatternToMatch = patternToMatch;
16 list ResultInstrs = resultInstrs;
17 }
18
19 // Pat - A simple (but common) form of a pattern, which produces a simple result
20 // not needing a full list.
21 class Pat : Pattern;
22
23 class Inst opcode, dag oopnds, dag iopnds, string asmstr,
24 list pattern> {
25 bits<8> Opcode = opcode;
26 dag OutOperands = oopnds;
27 dag InOperands = iopnds;
28 string AssemblyString = asmstr;
29 list Pattern = pattern;
30 }
31
32 def ops;
33 def outs;
34 def ins;
35
36 def set;
37
38 // Define registers
39 class Register {
40 string Name = n;
41 }
42
43 class RegisterClass regTypes, list regList> {
44 list RegTypes = regTypes;
45 list MemberList = regList;
46 }
47
48 def XMM0: Register<"xmm0">;
49 def XMM1: Register<"xmm1">;
50 def XMM2: Register<"xmm2">;
51 def XMM3: Register<"xmm3">;
52 def XMM4: Register<"xmm4">;
53 def XMM5: Register<"xmm5">;
54 def XMM6: Register<"xmm6">;
55 def XMM7: Register<"xmm7">;
56 def XMM8: Register<"xmm8">;
57 def XMM9: Register<"xmm9">;
58 def XMM10: Register<"xmm10">;
59 def XMM11: Register<"xmm11">;
60 def XMM12: Register<"xmm12">;
61 def XMM13: Register<"xmm13">;
62 def XMM14: Register<"xmm14">;
63 def XMM15: Register<"xmm15">;
64
65 def VR128 : RegisterClass<[v2i64, v2f64],
66 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
67 XMM8, XMM9, XMM10, XMM11,
68 XMM12, XMM13, XMM14, XMM15]>;
69
70 // Dummy for subst
71 def REGCLASS : RegisterClass<[], []>;
72 def MNEMONIC;
73
74 class decls {
75 // Dummy for foreach
76 dag pattern;
77 int operand;
78 }
79
80 def Decls : decls;
81
82 // Define intrinsics
83 def int_x86_sse2_add_ps : Intrinsic<"addps">;
84 def int_x86_sse2_add_pd : Intrinsic<"addpd">;
85 def INTRINSIC : Intrinsic<"Dummy">;
86 def bitconvert;
87
88 class MakePat patterns> : Pat;
89
90 class Base opcode, dag opnds, dag iopnds, string asmstr, Intrinsic intr,
91 list> patterns>
92 : Inst
93 !foreach(Decls.pattern, patterns[0],
94 !foreach(Decls.operand, Decls.pattern,
95 !subst(INTRINSIC, intr,
96 !subst(REGCLASS, VR128,
97 !subst(MNEMONIC, set, Decls.operand)))))>,
98 MakePat
99 !foreach(Decls.operand, Decls.pattern,
100 !subst(INTRINSIC, intr,
101 !subst(REGCLASS, VR128,
102 !subst(MNEMONIC, set, Decls.operand)))))>;
103
104 multiclass arith opcode, string asmstr, string intr, list> patterns> {
105 def PS : Base
106 !strconcat(asmstr, "\t$dst, $src1, $src2"), !cast(!subst("SUFFIX", "_ps", intr)), patterns>;
107
108 def PD : Base
109 !strconcat(asmstr, "\t$dst, $src1, $src2"), !cast(!subst("SUFFIX", "_pd", intr)), patterns>;
110 }
111
112 defm ADD : arith<0x58, "add", "int_x86_sse2_addSUFFIX",
113 // rr Patterns
114 [[(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))],
115 [(set REGCLASS:$dst, (bitconvert (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))),
116 (MNEMONIC REGCLASS:$dst, REGCLASS:$src)]]>;
117
118 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
119 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]