llvm.org GIT mirror llvm / 75dd57a
Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling There are a couple of (small) related changes here: 1. The printed name of the VRSAVE register has been changed from VRsave to vrsave in order to match the name accepted by GNU binutils. 2. Support for parsing vrsave has been added to the asm parser (it seems that there was no test case specifically covering this code, so I've added one). 3. The list of Altivec registers, which was common to all calling conventions, has been separated out. This allows us to define the base CSR lists, and then lists for each ABI with Altivec included. This allows SjLj, for example, to work correctly on non-Altivec targets without using unnatural definitions of the NoRegs CSR list. 4. VRSAVE is now always reserved on non-Darwin targets and all Altivec registers are reserved when Altivec is disabled. With these changes, it is now possible to compile a function containing __builtin_unwind_init() on Linux/PPC64 with debugging information. This did not work previously because GNU binutils assumes that all .cfi_offset offsets will be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned offset). This is not true for the vrsave register, however, because this register is used only on Darwin, GCC does not bother printing a .cfi_offset entry for it (even though there is a slot in the stack frame for it as specified by the ABI). This change allows us to do the same: we will also not print .cfi_offset directives for vrsave. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 6 years ago
6 changed file(s) with 331 addition(s) and 35 deletion(s). Raw diff Collapse all Expand all
751751 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
752752 IntVal = 9;
753753 return false;
754 } else if (Name.equals_lower("vrsave")) {
755 RegNo = PPC::VRSAVE;
756 IntVal = 256;
757 return false;
754758 } else if (Name.substr(0, 1).equals_lower("r") &&
755759 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
756760 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
104104 CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
105105 ]>;
106106
107 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
108 V28, V29, V30, V31)>;
109
107110 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
108111 R21, R22, R23, R24, R25, R26, R27, R28,
109112 R29, R30, R31, F14, F15, F16, F17, F18,
110113 F19, F20, F21, F22, F23, F24, F25, F26,
111 F27, F28, F29, F30, F31, CR2, CR3, CR4,
112 V20, V21, V22, V23, V24, V25, V26, V27,
113 V28, V29, V30, V31)>;
114 F27, F28, F29, F30, F31, CR2, CR3, CR4
115 )>;
114116
115 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, VRSAVE,
117 def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
118
119 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
116120 R21, R22, R23, R24, R25, R26, R27, R28,
117121 R29, R30, R31, F14, F15, F16, F17, F18,
118122 F19, F20, F21, F22, F23, F24, F25, F26,
119 F27, F28, F29, F30, F31, CR2, CR3, CR4,
120 V20, V21, V22, V23, V24, V25, V26, V27,
121 V28, V29, V30, V31)>;
123 F27, F28, F29, F30, F31, CR2, CR3, CR4
124 )>;
125
126 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
122127
123128 def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
124129 X21, X22, X23, X24, X25, X26, X27, X28,
125130 X29, X30, X31, F14, F15, F16, F17, F18,
126131 F19, F20, F21, F22, F23, F24, F25, F26,
127 F27, F28, F29, F30, F31, CR2, CR3, CR4,
128 V20, V21, V22, V23, V24, V25, V26, V27,
129 V28, V29, V30, V31)>;
132 F27, F28, F29, F30, F31, CR2, CR3, CR4
133 )>;
130134
131 def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, VRSAVE,
135 def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
136
137 def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
132138 X21, X22, X23, X24, X25, X26, X27, X28,
133139 X29, X30, X31, F14, F15, F16, F17, F18,
134140 F19, F20, F21, F22, F23, F24, F25, F26,
135 F27, F28, F29, F30, F31, CR2, CR3, CR4,
136 V20, V21, V22, V23, V24, V25, V26, V27,
137 V28, V29, V30, V31)>;
141 F27, F28, F29, F30, F31, CR2, CR3, CR4
142 )>;
138143
139 def CSR_NoRegs : CalleeSavedRegs<(add VRSAVE)>;
140 def CSR_NoRegs_Darwin : CalleeSavedRegs<(add)>;
141144
142 def CSR_NoRegs_Altivec : CalleeSavedRegs<(add (sequence "V%u", 0, 31), VRSAVE)>;
145 def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
143146
147 def CSR_NoRegs : CalleeSavedRegs<(add)>;
148
9090 const uint16_t*
9191 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
9292 if (Subtarget.isDarwinABI())
93 return Subtarget.isPPC64() ? CSR_Darwin64_SaveList :
94 CSR_Darwin32_SaveList;
95
96 return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList;
93 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
94 CSR_Darwin64_Altivec_SaveList :
95 CSR_Darwin64_SaveList) :
96 (Subtarget.hasAltivec() ?
97 CSR_Darwin32_Altivec_SaveList :
98 CSR_Darwin32_SaveList);
99
100 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
101 CSR_SVR464_Altivec_SaveList :
102 CSR_SVR464_SaveList) :
103 (Subtarget.hasAltivec() ?
104 CSR_SVR432_Altivec_SaveList :
105 CSR_SVR432_SaveList);
97106 }
98107
99108 const uint32_t*
100109 PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
101110 if (Subtarget.isDarwinABI())
102 return Subtarget.isPPC64() ? CSR_Darwin64_RegMask :
103 CSR_Darwin32_RegMask;
104
105 return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask;
111 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
112 CSR_Darwin64_Altivec_RegMask :
113 CSR_Darwin64_RegMask) :
114 (Subtarget.hasAltivec() ?
115 CSR_Darwin32_Altivec_RegMask :
116 CSR_Darwin32_RegMask);
117
118 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
119 CSR_SVR464_Altivec_RegMask :
120 CSR_SVR464_RegMask) :
121 (Subtarget.hasAltivec() ?
122 CSR_SVR432_Altivec_RegMask :
123 CSR_SVR432_RegMask);
106124 }
107125
108126 const uint32_t*
109127 PPCRegisterInfo::getNoPreservedMask() const {
110 // The naming here is inverted: The CSR_NoRegs_Altivec has the
111 // Altivec registers masked so that they're not saved and restored around
112 // instructions with this preserved mask.
113
114 if (!Subtarget.hasAltivec())
115 return CSR_NoRegs_Altivec_RegMask;
116
117 if (Subtarget.isDarwin())
118 return CSR_NoRegs_Darwin_RegMask;
119128 return CSR_NoRegs_RegMask;
120129 }
121130
144153 Reserved.set(PPC::LR8);
145154 Reserved.set(PPC::RM);
146155
156 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
157 Reserved.set(PPC::VRSAVE);
158
147159 // The SVR4 ABI reserves r2 and r13
148160 if (Subtarget.isSVR4ABI()) {
149161 Reserved.set(PPC::R2); // System-reserved register
168180
169181 if (PPCFI->needsFP(MF))
170182 Reserved.set(PPC::R31);
183
184 // Reserve Altivec registers when Altivec is unavailable.
185 if (!Subtarget.hasAltivec())
186 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
187 IE = PPC::VRRCRegClass.end(); I != IE; ++I)
188 Reserved.set(*I);
171189
172190 return Reserved;
173191 }
149149 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
150150
151151 // VRsave register
152 def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>;
152 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
153153
154154 // Carry bit. In the architecture this is really bit 0 of the XER register
155155 // (which really is SPR register 1); this is the only bit interesting to a
0 ; RUN: llc < %s | FileCheck %s
1 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
2 target triple = "powerpc64-unknown-linux-gnu"
3
4 ; Function Attrs: nounwind
5 define void @foo() #0 {
6 entry:
7 call void @llvm.eh.unwind.init(), !dbg !9
8 ret void, !dbg !10
9 }
10
11 ; CHECK: @foo
12 ; CHECK-NOT: .cfi_offset vrsave
13 ; CHECK: blr
14
15 ; Function Attrs: nounwind
16 declare void @llvm.eh.unwind.init() #0
17
18 attributes #0 = { nounwind }
19
20 !llvm.dbg.cu = !{!0}
21 !llvm.module.flags = !{!8}
22
23 !0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.4", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/unwind-dw2.c] [DW_LANG_C99]
24 !1 = metadata !{metadata !"/tmp/unwind-dw2.c", metadata !"/tmp"}
25 !2 = metadata !{i32 0}
26 !3 = metadata !{metadata !4}
27 !4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @foo, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
28 !5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [/tmp/unwind-dw2.c]
29 !6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
30 !7 = metadata !{null}
31 !8 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
32 !9 = metadata !{i32 2, i32 0, metadata !4, null}
33 !10 = metadata !{i32 3, i32 0, metadata !4, null}
0 # RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s
1
2 #CHECK: .cfi_startproc
3 #CHECK: .cfi_offset r0, 0
4 #CHECK: .cfi_offset r1, 8
5 #CHECK: .cfi_offset r2, 16
6 #CHECK: .cfi_offset r3, 24
7 #CHECK: .cfi_offset r4, 32
8 #CHECK: .cfi_offset r5, 40
9 #CHECK: .cfi_offset r6, 48
10 #CHECK: .cfi_offset r7, 56
11 #CHECK: .cfi_offset r8, 64
12 #CHECK: .cfi_offset r9, 72
13 #CHECK: .cfi_offset r10, 80
14 #CHECK: .cfi_offset r11, 88
15 #CHECK: .cfi_offset r12, 96
16 #CHECK: .cfi_offset r13, 104
17 #CHECK: .cfi_offset r14, 112
18 #CHECK: .cfi_offset r15, 120
19 #CHECK: .cfi_offset r16, 128
20 #CHECK: .cfi_offset r17, 136
21 #CHECK: .cfi_offset r18, 144
22 #CHECK: .cfi_offset r19, 152
23 #CHECK: .cfi_offset r20, 160
24 #CHECK: .cfi_offset r21, 168
25 #CHECK: .cfi_offset r22, 176
26 #CHECK: .cfi_offset r22, 184
27 #CHECK: .cfi_offset r23, 192
28 #CHECK: .cfi_offset r24, 200
29 #CHECK: .cfi_offset r25, 208
30 #CHECK: .cfi_offset r26, 216
31 #CHECK: .cfi_offset r27, 224
32 #CHECK: .cfi_offset r28, 232
33 #CHECK: .cfi_offset r29, 240
34 #CHECK: .cfi_offset r30, 248
35 #CHECK: .cfi_offset r31, 256
36
37 #CHECK: .cfi_offset f0, 300
38 #CHECK: .cfi_offset f1, 308
39 #CHECK: .cfi_offset f2, 316
40 #CHECK: .cfi_offset f3, 324
41 #CHECK: .cfi_offset f4, 332
42 #CHECK: .cfi_offset f5, 340
43 #CHECK: .cfi_offset f6, 348
44 #CHECK: .cfi_offset f7, 356
45 #CHECK: .cfi_offset f8, 364
46 #CHECK: .cfi_offset f9, 372
47 #CHECK: .cfi_offset f10, 380
48 #CHECK: .cfi_offset f11, 388
49 #CHECK: .cfi_offset f12, 396
50 #CHECK: .cfi_offset f13, 404
51 #CHECK: .cfi_offset f14, 412
52 #CHECK: .cfi_offset f15, 420
53 #CHECK: .cfi_offset f16, 428
54 #CHECK: .cfi_offset f17, 436
55 #CHECK: .cfi_offset f18, 444
56 #CHECK: .cfi_offset f19, 452
57 #CHECK: .cfi_offset f20, 460
58 #CHECK: .cfi_offset f21, 468
59 #CHECK: .cfi_offset f22, 476
60 #CHECK: .cfi_offset f22, 484
61 #CHECK: .cfi_offset f23, 492
62 #CHECK: .cfi_offset f24, 500
63 #CHECK: .cfi_offset f25, 508
64 #CHECK: .cfi_offset f26, 516
65 #CHECK: .cfi_offset f27, 524
66 #CHECK: .cfi_offset f28, 532
67 #CHECK: .cfi_offset f29, 540
68 #CHECK: .cfi_offset f30, 548
69 #CHECK: .cfi_offset f31, 556
70
71 #CHECK: .cfi_offset lr, 600
72 #CHECK: .cfi_offset ctr, 608
73 #CHECK: .cfi_offset vrsave, 616
74
75 #CHECK: .cfi_offset cr0, 620
76 #CHECK: .cfi_offset cr1, 621
77 #CHECK: .cfi_offset cr2, 622
78 #CHECK: .cfi_offset cr3, 623
79 #CHECK: .cfi_offset cr4, 624
80 #CHECK: .cfi_offset cr5, 625
81 #CHECK: .cfi_offset cr6, 626
82 #CHECK: .cfi_offset cr7, 627
83
84 #CHECK: .cfi_offset v0, 700
85 #CHECK: .cfi_offset v1, 716
86 #CHECK: .cfi_offset v2, 732
87 #CHECK: .cfi_offset v3, 748
88 #CHECK: .cfi_offset v4, 764
89 #CHECK: .cfi_offset v5, 780
90 #CHECK: .cfi_offset v6, 796
91 #CHECK: .cfi_offset v7, 812
92 #CHECK: .cfi_offset v8, 828
93 #CHECK: .cfi_offset v9, 844
94 #CHECK: .cfi_offset v10, 860
95 #CHECK: .cfi_offset v11, 876
96 #CHECK: .cfi_offset v12, 892
97 #CHECK: .cfi_offset v13, 908
98 #CHECK: .cfi_offset v14, 924
99 #CHECK: .cfi_offset v15, 940
100 #CHECK: .cfi_offset v16, 956
101 #CHECK: .cfi_offset v17, 972
102 #CHECK: .cfi_offset v18, 988
103 #CHECK: .cfi_offset v19, 1004
104 #CHECK: .cfi_offset v20, 1020
105 #CHECK: .cfi_offset v21, 1036
106 #CHECK: .cfi_offset v22, 1052
107 #CHECK: .cfi_offset v22, 1068
108 #CHECK: .cfi_offset v23, 1084
109 #CHECK: .cfi_offset v24, 1100
110 #CHECK: .cfi_offset v25, 1116
111 #CHECK: .cfi_offset v26, 1132
112 #CHECK: .cfi_offset v27, 1148
113 #CHECK: .cfi_offset v28, 1164
114 #CHECK: .cfi_offset v29, 1180
115 #CHECK: .cfi_offset v30, 1196
116 #CHECK: .cfi_offset v31, 1212
117 #CHECK: .cfi_endproc
118
119 .cfi_startproc
120 .cfi_offset r0,0
121 .cfi_offset r1,8
122 .cfi_offset r2,16
123 .cfi_offset r3,24
124 .cfi_offset r4,32
125 .cfi_offset r5,40
126 .cfi_offset r6,48
127 .cfi_offset r7,56
128 .cfi_offset r8,64
129 .cfi_offset r9,72
130 .cfi_offset r10,80
131 .cfi_offset r11,88
132 .cfi_offset r12,96
133 .cfi_offset r13,104
134 .cfi_offset r14,112
135 .cfi_offset r15,120
136 .cfi_offset r16,128
137 .cfi_offset r17,136
138 .cfi_offset r18,144
139 .cfi_offset r19,152
140 .cfi_offset r20,160
141 .cfi_offset r21,168
142 .cfi_offset r22,176
143 .cfi_offset r22,184
144 .cfi_offset r23,192
145 .cfi_offset r24,200
146 .cfi_offset r25,208
147 .cfi_offset r26,216
148 .cfi_offset r27,224
149 .cfi_offset r28,232
150 .cfi_offset r29,240
151 .cfi_offset r30,248
152 .cfi_offset r31,256
153
154 .cfi_offset f0,300
155 .cfi_offset f1,308
156 .cfi_offset f2,316
157 .cfi_offset f3,324
158 .cfi_offset f4,332
159 .cfi_offset f5,340
160 .cfi_offset f6,348
161 .cfi_offset f7,356
162 .cfi_offset f8,364
163 .cfi_offset f9,372
164 .cfi_offset f10,380
165 .cfi_offset f11,388
166 .cfi_offset f12,396
167 .cfi_offset f13,404
168 .cfi_offset f14,412
169 .cfi_offset f15,420
170 .cfi_offset f16,428
171 .cfi_offset f17,436
172 .cfi_offset f18,444
173 .cfi_offset f19,452
174 .cfi_offset f20,460
175 .cfi_offset f21,468
176 .cfi_offset f22,476
177 .cfi_offset f22,484
178 .cfi_offset f23,492
179 .cfi_offset f24,500
180 .cfi_offset f25,508
181 .cfi_offset f26,516
182 .cfi_offset f27,524
183 .cfi_offset f28,532
184 .cfi_offset f29,540
185 .cfi_offset f30,548
186 .cfi_offset f31,556
187
188 .cfi_offset lr,600
189 .cfi_offset ctr,608
190 .cfi_offset vrsave,616
191 .cfi_offset cr0,620
192 .cfi_offset cr1,621
193 .cfi_offset cr2,622
194 .cfi_offset cr3,623
195 .cfi_offset cr4,624
196 .cfi_offset cr5,625
197 .cfi_offset cr6,626
198 .cfi_offset cr7,627
199
200 .cfi_offset v0,700
201 .cfi_offset v1,716
202 .cfi_offset v2,732
203 .cfi_offset v3,748
204 .cfi_offset v4,764
205 .cfi_offset v5,780
206 .cfi_offset v6,796
207 .cfi_offset v7,812
208 .cfi_offset v8,828
209 .cfi_offset v9,844
210 .cfi_offset v10,860
211 .cfi_offset v11,876
212 .cfi_offset v12,892
213 .cfi_offset v13,908
214 .cfi_offset v14,924
215 .cfi_offset v15,940
216 .cfi_offset v16,956
217 .cfi_offset v17,972
218 .cfi_offset v18,988
219 .cfi_offset v19,1004
220 .cfi_offset v20,1020
221 .cfi_offset v21,1036
222 .cfi_offset v22,1052
223 .cfi_offset v22,1068
224 .cfi_offset v23,1084
225 .cfi_offset v24,1100
226 .cfi_offset v25,1116
227 .cfi_offset v26,1132
228 .cfi_offset v27,1148
229 .cfi_offset v28,1164
230 .cfi_offset v29,1180
231 .cfi_offset v30,1196
232 .cfi_offset v31,1212
233
234 .cfi_endproc