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[AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsia This mode is just like -mcmodel=small except that it moves the thread pointer from TPIDR_EL0 to TPIDR_EL1. Patch by Roland McGrath. Differential Revision: https://reviews.llvm.org/D31624 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299462 91177308-0d34-0410-b5e6-96231b3b80d8 Petr Hosek 2 years ago
9 changed file(s) with 51 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
891891 }
892892 case AArch64::MOVbaseTLS: {
893893 unsigned DstReg = MI.getOperand(0).getReg();
894 auto SysReg = AArch64SysReg::TPIDR_EL0;
895 MachineFunction *MF = MBB.getParent();
896 if (MF->getTarget().getTargetTriple().isOSFuchsia() &&
897 MF->getTarget().getCodeModel() == CodeModel::Kernel)
898 SysReg = AArch64SysReg::TPIDR_EL1;
894899 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
895 .addImm(AArch64SysReg::TPIDR_EL0);
900 .addImm(SysReg);
896901 MI.eraseFromParent();
897902 return true;
898903 }
457457
458458 // MachO still uses GOT for large code-model accesses, but ELF requires
459459 // movz/movk sequences, which FastISel doesn't handle yet.
460 if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
460 if (!Subtarget->useSmallAddressing() && !Subtarget->isTargetMachO())
461461 return 0;
462462
463463 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
31463146 return false;
31473147
31483148 CodeModel::Model CM = TM.getCodeModel();
3149 // Only support the small and large code model.
3150 if (CM != CodeModel::Small && CM != CodeModel::Large)
3149 // Only support the small-addressing and large code models.
3150 if (CM != CodeModel::Large && !Subtarget->useSmallAddressing())
31513151 return false;
31523152
31533153 // FIXME: Add large code model support for ELF.
31983198
31993199 // Issue the call.
32003200 MachineInstrBuilder MIB;
3201 if (CM == CodeModel::Small) {
3201 if (Subtarget->useSmallAddressing()) {
32023202 const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
32033203 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II);
32043204 if (Symbol)
35713571 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
35723572 SelectionDAG &DAG) const {
35733573 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3574 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3574 assert(Subtarget->useSmallAddressing() &&
35753575 "ELF TLS only supported in small memory model");
35763576 // Different choices can be made for the maximum size of the TLS area for a
35773577 // module. For the small address model, the default TLS size is 16MiB and the
146146 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
147147 return AArch64II::MO_GOT;
148148
149 // The small code mode's direct accesses use ADRP, which cannot necessarily
150 // produce the value 0 (if the code is above 4GB).
151 if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage())
149 // The small code model's direct accesses use ADRP, which cannot
150 // necessarily produce the value 0 (if the code is above 4GB).
151 if (useSmallAddressing() && GV->hasExternalWeakLinkage())
152152 return AArch64II::MO_GOT;
153153
154154 return AArch64II::MO_NO_FLAG;
249249
250250 bool useAA() const override { return UseAA; }
251251
252 bool useSmallAddressing() const {
253 switch (TLInfo.getTargetMachine().getCodeModel()) {
254 case CodeModel::Kernel:
255 // Kernel is currently allowed only for Fuchsia targets,
256 // where it is the same as Small for almost all purposes.
257 case CodeModel::Small:
258 return true;
259 default:
260 return false;
261 }
262 }
263
252264 /// ParseSubtargetFeatures - Parses features string setting specified
253265 /// subtarget options. Definition of function is auto generated by tblgen.
254266 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
8383 // no matter how far away they are.
8484 else if (CM == CodeModel::JITDefault)
8585 CM = CodeModel::Large;
86 else if (CM != CodeModel::Small && CM != CodeModel::Large)
87 report_fatal_error(
88 "Only small and large code models are allowed on AArch64");
86 else if (CM != CodeModel::Small && CM != CodeModel::Large) {
87 if (!TT.isOSFuchsia())
88 report_fatal_error(
89 "Only small and large code models are allowed on AArch64");
90 else if (CM != CodeModel::Kernel)
91 report_fatal_error(
92 "Only small, kernel, and large code models are allowed on AArch64");
93 }
8994 }
9095
9196 static MCInstPrinter *createAArch64MCInstPrinter(const Triple &T,
0 ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
1 ; RUN: llc < %s -mtriple=aarch64-fuchsia | FileCheck %s
2 ; RUN: llc < %s -mtriple=aarch64-fuchsia -code-model=kernel | FileCheck --check-prefix=FUCHSIA-KERNEL %s
13
24 ; Function Attrs: nounwind readnone
35 declare i8* @llvm.thread.pointer() #1
57 define i8* @thread_pointer() {
68 ; CHECK: thread_pointer:
79 ; CHECK: mrs {{x[0-9]+}}, TPIDR_EL0
10 ; FUCHSIA-KERNEL: thread_pointer:
11 ; FUCHSIA-KERNEL: mrs {{x[0-9]+}}, TPIDR_EL1
812 %1 = tail call i8* @llvm.thread.pointer()
913 ret i8* %1
1014 }
11 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
22 ; RUN: llc -mtriple=arm64-linux-gnu -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-PIC
33 ; RUN: llc -mtriple=arm64-linux-gnu -O0 -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST-PIC
4 ; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel -o - %s -mcpu=cyclone | FileCheck %s
5 ; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel -o - %s -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
6 ; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-PIC
7 ; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel -O0 -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST-PIC
48
59 @var8 = external global i8, align 1
610 @var16 = external global i16, align 2
0 ; Test target-specific stack cookie location.
11 ; RUN: llc -mtriple=aarch64-linux-android < %s -o - | FileCheck --check-prefix=ANDROID-AARCH64 %s
2 ; RUN: llc -mtriple=aarch64-fuchsia < %s -o - | FileCheck --check-prefix=FUCHSIA-AARCH64 %s
2 ; RUN: llc -mtriple=aarch64-fuchsia < %s -o - | FileCheck --check-prefixes=FUCHSIA-AARCH64-COMMON,FUCHSIA-AARCH64-USER %s
3 ; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel < %s -o - | FileCheck --check-prefixes=FUCHSIA-AARCH64-COMMON,FUCHSIA-AARCH64-KERNEL %s
34
45 define void @_Z1fv() sspreq {
56 entry:
1819 ; ANDROID-AARCH64: ldr [[D:.*]], [sp,
1920 ; ANDROID-AARCH64: cmp [[C]], [[D]]
2021
21 ; FUCHSIA-AARCH64: mrs [[A:.*]], TPIDR_EL0
22 ; FUCHSIA-AARCH64: ldur [[B:.*]], {{\[}}[[A]], #-16]
23 ; FUCHSIA-AARCH64: str [[B]], [sp,
24 ; FUCHSIA-AARCH64: ldur [[C:.*]], {{\[}}[[A]], #-16]
25 ; FUCHSIA-AARCH64: ldr [[D:.*]], [sp,
26 ; FUCHSIA-AARCH64: cmp [[C]], [[D]]
22 ; FUCHSIA-AARCH64-USER: mrs [[A:.*]], TPIDR_EL0
23 ; FUCHSIA-AARCH64-KERNEL: mrs [[A:.*]], TPIDR_EL1
24 ; FUCHSIA-AARCH64-COMMON: ldur [[B:.*]], {{\[}}[[A]], #-16]
25 ; FUCHSIA-AARCH64-COMMON: str [[B]], [sp,
26 ; FUCHSIA-AARCH64-COMMON: ldur [[C:.*]], {{\[}}[[A]], #-16]
27 ; FUCHSIA-AARCH64-COMMON: ldr [[D:.*]], [sp,
28 ; FUCHSIA-AARCH64-COMMON: cmp [[C]], [[D]]