llvm.org GIT mirror llvm / 75b41f1
Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129742 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 9 years ago
2 changed file(s) with 573 addition(s) and 372 deletion(s). Raw diff Collapse all Expand all
22212221 }
22222222 }
22232223
2224 if (DefAlign < 8 && Subtarget.isCortexA9())
2225 switch (DefTID.getOpcode()) {
2226 default: break;
2227 case ARM::VLD1q8:
2228 case ARM::VLD1q16:
2229 case ARM::VLD1q32:
2230 case ARM::VLD1q64:
2231 case ARM::VLD1q8_UPD:
2232 case ARM::VLD1q16_UPD:
2233 case ARM::VLD1q32_UPD:
2234 case ARM::VLD1q64_UPD:
2235 case ARM::VLD2d8:
2236 case ARM::VLD2d16:
2237 case ARM::VLD2d32:
2238 case ARM::VLD2q8:
2239 case ARM::VLD2q16:
2240 case ARM::VLD2q32:
2241 case ARM::VLD2d8_UPD:
2242 case ARM::VLD2d16_UPD:
2243 case ARM::VLD2d32_UPD:
2244 case ARM::VLD2q8_UPD:
2245 case ARM::VLD2q16_UPD:
2246 case ARM::VLD2q32_UPD:
2247 case ARM::VLD3d8:
2248 case ARM::VLD3d16:
2249 case ARM::VLD3d32:
2250 case ARM::VLD1d64T:
2251 case ARM::VLD3d8_UPD:
2252 case ARM::VLD3d16_UPD:
2253 case ARM::VLD3d32_UPD:
2254 case ARM::VLD1d64T_UPD:
2255 case ARM::VLD3q8_UPD:
2256 case ARM::VLD3q16_UPD:
2257 case ARM::VLD3q32_UPD:
2258 case ARM::VLD4d8:
2259 case ARM::VLD4d16:
2260 case ARM::VLD4d32:
2261 case ARM::VLD1d64Q:
2262 case ARM::VLD4d8_UPD:
2263 case ARM::VLD4d16_UPD:
2264 case ARM::VLD4d32_UPD:
2265 case ARM::VLD1d64Q_UPD:
2266 case ARM::VLD4q8_UPD:
2267 case ARM::VLD4q16_UPD:
2268 case ARM::VLD4q32_UPD:
2269 case ARM::VLD1DUPq8:
2270 case ARM::VLD1DUPq16:
2271 case ARM::VLD1DUPq32:
2272 case ARM::VLD1DUPq8_UPD:
2273 case ARM::VLD1DUPq16_UPD:
2274 case ARM::VLD1DUPq32_UPD:
2275 case ARM::VLD2DUPd8:
2276 case ARM::VLD2DUPd16:
2277 case ARM::VLD2DUPd32:
2278 case ARM::VLD2DUPd8_UPD:
2279 case ARM::VLD2DUPd16_UPD:
2280 case ARM::VLD2DUPd32_UPD:
2281 case ARM::VLD4DUPd8:
2282 case ARM::VLD4DUPd16:
2283 case ARM::VLD4DUPd32:
2284 case ARM::VLD4DUPd8_UPD:
2285 case ARM::VLD4DUPd16_UPD:
2286 case ARM::VLD4DUPd32_UPD:
2287 case ARM::VLD1LNd8:
2288 case ARM::VLD1LNd16:
2289 case ARM::VLD1LNd32:
2290 case ARM::VLD1LNd8_UPD:
2291 case ARM::VLD1LNd16_UPD:
2292 case ARM::VLD1LNd32_UPD:
2293 case ARM::VLD2LNd8:
2294 case ARM::VLD2LNd16:
2295 case ARM::VLD2LNd32:
2296 case ARM::VLD2LNq16:
2297 case ARM::VLD2LNq32:
2298 case ARM::VLD2LNd8_UPD:
2299 case ARM::VLD2LNd16_UPD:
2300 case ARM::VLD2LNd32_UPD:
2301 case ARM::VLD2LNq16_UPD:
2302 case ARM::VLD2LNq32_UPD:
2303 case ARM::VLD4LNd8:
2304 case ARM::VLD4LNd16:
2305 case ARM::VLD4LNd32:
2306 case ARM::VLD4LNq16:
2307 case ARM::VLD4LNq32:
2308 case ARM::VLD4LNd8_UPD:
2309 case ARM::VLD4LNd16_UPD:
2310 case ARM::VLD4LNd32_UPD:
2311 case ARM::VLD4LNq16_UPD:
2312 case ARM::VLD4LNq32_UPD:
2313 // If the address is not 64-bit aligned, the latencies of these
2314 // instructions increases by one.
2315 ++Latency;
2316 break;
2317 }
2318
22242319 return Latency;
22252320 }
22262321
22872382 }
22882383 }
22892384
2385 if (DefAlign < 8 && Subtarget.isCortexA9())
2386 switch (DefTID.getOpcode()) {
2387 default: break;
2388 case ARM::VLD1q8Pseudo:
2389 case ARM::VLD1q16Pseudo:
2390 case ARM::VLD1q32Pseudo:
2391 case ARM::VLD1q64Pseudo:
2392 case ARM::VLD1q8Pseudo_UPD:
2393 case ARM::VLD1q16Pseudo_UPD:
2394 case ARM::VLD1q32Pseudo_UPD:
2395 case ARM::VLD1q64Pseudo_UPD:
2396 case ARM::VLD2d8Pseudo:
2397 case ARM::VLD2d16Pseudo:
2398 case ARM::VLD2d32Pseudo:
2399 case ARM::VLD2q8Pseudo:
2400 case ARM::VLD2q16Pseudo:
2401 case ARM::VLD2q32Pseudo:
2402 case ARM::VLD2d8Pseudo_UPD:
2403 case ARM::VLD2d16Pseudo_UPD:
2404 case ARM::VLD2d32Pseudo_UPD:
2405 case ARM::VLD2q8Pseudo_UPD:
2406 case ARM::VLD2q16Pseudo_UPD:
2407 case ARM::VLD2q32Pseudo_UPD:
2408 case ARM::VLD3d8Pseudo:
2409 case ARM::VLD3d16Pseudo:
2410 case ARM::VLD3d32Pseudo:
2411 case ARM::VLD1d64TPseudo:
2412 case ARM::VLD3d8Pseudo_UPD:
2413 case ARM::VLD3d16Pseudo_UPD:
2414 case ARM::VLD3d32Pseudo_UPD:
2415 case ARM::VLD1d64TPseudo_UPD:
2416 case ARM::VLD3q8Pseudo_UPD:
2417 case ARM::VLD3q16Pseudo_UPD:
2418 case ARM::VLD3q32Pseudo_UPD:
2419 case ARM::VLD3q8oddPseudo:
2420 case ARM::VLD3q16oddPseudo:
2421 case ARM::VLD3q32oddPseudo:
2422 case ARM::VLD3q8oddPseudo_UPD:
2423 case ARM::VLD3q16oddPseudo_UPD:
2424 case ARM::VLD3q32oddPseudo_UPD:
2425 case ARM::VLD4d8Pseudo:
2426 case ARM::VLD4d16Pseudo:
2427 case ARM::VLD4d32Pseudo:
2428 case ARM::VLD1d64QPseudo:
2429 case ARM::VLD4d8Pseudo_UPD:
2430 case ARM::VLD4d16Pseudo_UPD:
2431 case ARM::VLD4d32Pseudo_UPD:
2432 case ARM::VLD1d64QPseudo_UPD:
2433 case ARM::VLD4q8Pseudo_UPD:
2434 case ARM::VLD4q16Pseudo_UPD:
2435 case ARM::VLD4q32Pseudo_UPD:
2436 case ARM::VLD4q8oddPseudo:
2437 case ARM::VLD4q16oddPseudo:
2438 case ARM::VLD4q32oddPseudo:
2439 case ARM::VLD4q8oddPseudo_UPD:
2440 case ARM::VLD4q16oddPseudo_UPD:
2441 case ARM::VLD4q32oddPseudo_UPD:
2442 case ARM::VLD1DUPq8Pseudo:
2443 case ARM::VLD1DUPq16Pseudo:
2444 case ARM::VLD1DUPq32Pseudo:
2445 case ARM::VLD1DUPq8Pseudo_UPD:
2446 case ARM::VLD1DUPq16Pseudo_UPD:
2447 case ARM::VLD1DUPq32Pseudo_UPD:
2448 case ARM::VLD2DUPd8Pseudo:
2449 case ARM::VLD2DUPd16Pseudo:
2450 case ARM::VLD2DUPd32Pseudo:
2451 case ARM::VLD2DUPd8Pseudo_UPD:
2452 case ARM::VLD2DUPd16Pseudo_UPD:
2453 case ARM::VLD2DUPd32Pseudo_UPD:
2454 case ARM::VLD4DUPd8Pseudo:
2455 case ARM::VLD4DUPd16Pseudo:
2456 case ARM::VLD4DUPd32Pseudo:
2457 case ARM::VLD4DUPd8Pseudo_UPD:
2458 case ARM::VLD4DUPd16Pseudo_UPD:
2459 case ARM::VLD4DUPd32Pseudo_UPD:
2460 case ARM::VLD1LNq8Pseudo:
2461 case ARM::VLD1LNq16Pseudo:
2462 case ARM::VLD1LNq32Pseudo:
2463 case ARM::VLD1LNq8Pseudo_UPD:
2464 case ARM::VLD1LNq16Pseudo_UPD:
2465 case ARM::VLD1LNq32Pseudo_UPD:
2466 case ARM::VLD2LNd8Pseudo:
2467 case ARM::VLD2LNd16Pseudo:
2468 case ARM::VLD2LNd32Pseudo:
2469 case ARM::VLD2LNq16Pseudo:
2470 case ARM::VLD2LNq32Pseudo:
2471 case ARM::VLD2LNd8Pseudo_UPD:
2472 case ARM::VLD2LNd16Pseudo_UPD:
2473 case ARM::VLD2LNd32Pseudo_UPD:
2474 case ARM::VLD2LNq16Pseudo_UPD:
2475 case ARM::VLD2LNq32Pseudo_UPD:
2476 case ARM::VLD4LNd8Pseudo:
2477 case ARM::VLD4LNd16Pseudo:
2478 case ARM::VLD4LNd32Pseudo:
2479 case ARM::VLD4LNq16Pseudo:
2480 case ARM::VLD4LNq32Pseudo:
2481 case ARM::VLD4LNd8Pseudo_UPD:
2482 case ARM::VLD4LNd16Pseudo_UPD:
2483 case ARM::VLD4LNd32Pseudo_UPD:
2484 case ARM::VLD4LNq16Pseudo_UPD:
2485 case ARM::VLD4LNq32Pseudo_UPD:
2486 // If the address is not 64-bit aligned, the latencies of these
2487 // instructions increases by one.
2488 ++Latency;
2489 break;
2490 }
2491
22902492 return Latency;
22912493 }
22922494
740740 InstrStage<1, [A9_LSUnit]>], [2, 1, 1, 1]>,
741741 // NEON
742742 // VLD1
743 // FIXME: Conservatively assume insufficent alignment.
744743 InstrItinData,
745744 InstrStage<1, [A9_MUX0], 0>,
746745 InstrStage<1, [A9_DRegsN], 0, Required>,
747 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
748 InstrStage<2, [A9_NPipe], 0>,
749 InstrStage<2, [A9_LSUnit]>],
750 [2, 1]>,
746 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
747 InstrStage<1, [A9_NPipe], 0>,
748 InstrStage<1, [A9_LSUnit]>],
749 [1, 1]>,
751750 // VLD1x2
752751 InstrItinData,
753752 InstrStage<1, [A9_MUX0], 0>,
754753 InstrStage<1, [A9_DRegsN], 0, Required>,
755 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
756 InstrStage<2, [A9_NPipe], 0>,
757 InstrStage<2, [A9_LSUnit]>],
758 [2, 2, 1]>,
754 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
755 InstrStage<1, [A9_NPipe], 0>,
756 InstrStage<1, [A9_LSUnit]>],
757 [1, 1, 1]>,
759758 // VLD1x3
760759 InstrItinData,
761760 InstrStage<1, [A9_MUX0], 0>,
762761 InstrStage<1, [A9_DRegsN], 0, Required>,
763 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
762 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
763 InstrStage<2, [A9_NPipe], 0>,
764 InstrStage<2, [A9_LSUnit]>],
765 [1, 1, 2, 1]>,
766 // VLD1x4
767 InstrItinData,
768 InstrStage<1, [A9_MUX0], 0>,
769 InstrStage<1, [A9_DRegsN], 0, Required>,
770 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
771 InstrStage<2, [A9_NPipe], 0>,
772 InstrStage<2, [A9_LSUnit]>],
773 [1, 1, 2, 2, 1]>,
774 // VLD1u
775 InstrItinData,
776 InstrStage<1, [A9_MUX0], 0>,
777 InstrStage<1, [A9_DRegsN], 0, Required>,
778 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
779 InstrStage<1, [A9_NPipe], 0>,
780 InstrStage<1, [A9_LSUnit]>],
781 [1, 2, 1]>,
782 // VLD1x2u
783 InstrItinData,
784 InstrStage<1, [A9_MUX0], 0>,
785 InstrStage<1, [A9_DRegsN], 0, Required>,
786 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
787 InstrStage<1, [A9_NPipe], 0>,
788 InstrStage<1, [A9_LSUnit]>],
789 [1, 1, 2, 1]>,
790 // VLD1x3u
791 InstrItinData,
792 InstrStage<1, [A9_MUX0], 0>,
793 InstrStage<1, [A9_DRegsN], 0, Required>,
794 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
795 InstrStage<2, [A9_NPipe], 0>,
796 InstrStage<2, [A9_LSUnit]>],
797 [1, 1, 2, 2, 1]>,
798 // VLD1x4u
799 InstrItinData,
800 InstrStage<1, [A9_MUX0], 0>,
801 InstrStage<1, [A9_DRegsN], 0, Required>,
802 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
803 InstrStage<2, [A9_NPipe], 0>,
804 InstrStage<2, [A9_LSUnit]>],
805 [1, 1, 2, 2, 2, 1]>,
806 //
807 // VLD1ln
808 InstrItinData,
809 InstrStage<1, [A9_MUX0], 0>,
810 InstrStage<1, [A9_DRegsN], 0, Required>,
811 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
812 InstrStage<2, [A9_NPipe], 0>,
813 InstrStage<2, [A9_LSUnit]>],
814 [3, 1, 1, 1]>,
815 //
816 // VLD1lnu
817 InstrItinData,
818 InstrStage<1, [A9_MUX0], 0>,
819 InstrStage<1, [A9_DRegsN], 0, Required>,
820 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
821 InstrStage<2, [A9_NPipe], 0>,
822 InstrStage<2, [A9_LSUnit]>],
823 [3, 2, 1, 1, 1, 1]>,
824 //
825 // VLD1dup
826 InstrItinData,
827 InstrStage<1, [A9_MUX0], 0>,
828 InstrStage<1, [A9_DRegsN], 0, Required>,
829 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
830 InstrStage<1, [A9_NPipe], 0>,
831 InstrStage<1, [A9_LSUnit]>],
832 [2, 1]>,
833 //
834 // VLD1dupu
835 InstrItinData,
836 InstrStage<1, [A9_MUX0], 0>,
837 InstrStage<1, [A9_DRegsN], 0, Required>,
838 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
839 InstrStage<1, [A9_NPipe], 0>,
840 InstrStage<1, [A9_LSUnit]>],
841 [2, 2, 1, 1]>,
842 //
843 // VLD2
844 InstrItinData,
845 InstrStage<1, [A9_MUX0], 0>,
846 InstrStage<1, [A9_DRegsN], 0, Required>,
847 // Extra latency cycles since wbck is 7 cycles
848 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
849 InstrStage<1, [A9_NPipe], 0>,
850 InstrStage<1, [A9_LSUnit]>],
851 [2, 2, 1]>,
852 //
853 // VLD2x2
854 InstrItinData,
855 InstrStage<1, [A9_MUX0], 0>,
856 InstrStage<1, [A9_DRegsN], 0, Required>,
857 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
858 InstrStage<2, [A9_NPipe], 0>,
859 InstrStage<2, [A9_LSUnit]>],
860 [2, 3, 2, 3, 1]>,
861 //
862 // VLD2ln
863 InstrItinData,
864 InstrStage<1, [A9_MUX0], 0>,
865 InstrStage<1, [A9_DRegsN], 0, Required>,
866 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
867 InstrStage<2, [A9_NPipe], 0>,
868 InstrStage<2, [A9_LSUnit]>],
869 [3, 3, 1, 1, 1, 1]>,
870 //
871 // VLD2u
872 InstrItinData,
873 InstrStage<1, [A9_MUX0], 0>,
874 InstrStage<1, [A9_DRegsN], 0, Required>,
875 // Extra latency cycles since wbck is 7 cycles
876 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
877 InstrStage<1, [A9_NPipe], 0>,
878 InstrStage<1, [A9_LSUnit]>],
879 [2, 2, 2, 1, 1, 1]>,
880 //
881 // VLD2x2u
882 InstrItinData,
883 InstrStage<1, [A9_MUX0], 0>,
884 InstrStage<1, [A9_DRegsN], 0, Required>,
885 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
886 InstrStage<2, [A9_NPipe], 0>,
887 InstrStage<2, [A9_LSUnit]>],
888 [2, 3, 2, 3, 2, 1]>,
889 //
890 // VLD2lnu
891 InstrItinData,
892 InstrStage<1, [A9_MUX0], 0>,
893 InstrStage<1, [A9_DRegsN], 0, Required>,
894 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
895 InstrStage<2, [A9_NPipe], 0>,
896 InstrStage<2, [A9_LSUnit]>],
897 [3, 3, 2, 1, 1, 1, 1, 1]>,
898 //
899 // VLD2dup
900 InstrItinData,
901 InstrStage<1, [A9_MUX0], 0>,
902 InstrStage<1, [A9_DRegsN], 0, Required>,
903 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
904 InstrStage<1, [A9_NPipe], 0>,
905 InstrStage<1, [A9_LSUnit]>],
906 [2, 2, 1]>,
907 //
908 // VLD2dupu
909 InstrItinData,
910 InstrStage<1, [A9_MUX0], 0>,
911 InstrStage<1, [A9_DRegsN], 0, Required>,
912 InstrStage<7, [A9_DRegsVFP], 0, Reserved>,
913 InstrStage<1, [A9_NPipe], 0>,
914 InstrStage<1, [A9_LSUnit]>],
915 [2, 2, 2, 1, 1]>,
916 //
917 // VLD3
918 InstrItinData,
919 InstrStage<1, [A9_MUX0], 0>,
920 InstrStage<1, [A9_DRegsN], 0, Required>,
921 InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
764922 InstrStage<3, [A9_NPipe], 0>,
765923 InstrStage<3, [A9_LSUnit]>],
766 [2, 2, 3, 1]>,
767 // VLD1x4
768 InstrItinData,
769 InstrStage<1, [A9_MUX0], 0>,
770 InstrStage<1, [A9_DRegsN], 0, Required>,
771 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
772 InstrStage<3, [A9_NPipe], 0>,
773 InstrStage<3, [A9_LSUnit]>],
774 [2, 2, 3, 3, 1]>,
775 // VLD1u
776 InstrItinData,
777 InstrStage<1, [A9_MUX0], 0>,
778 InstrStage<1, [A9_DRegsN], 0, Required>,
779 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
780 InstrStage<2, [A9_NPipe], 0>,
781 InstrStage<2, [A9_LSUnit]>],
782 [2, 2, 1]>,
783 // VLD1x2u
784 InstrItinData,
785 InstrStage<1, [A9_MUX0], 0>,
786 InstrStage<1, [A9_DRegsN], 0, Required>,
787 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
788 InstrStage<2, [A9_NPipe], 0>,
789 InstrStage<2, [A9_LSUnit]>],
790 [2, 2, 2, 1]>,
791 // VLD1x3u
792 InstrItinData,
793 InstrStage<1, [A9_MUX0], 0>,
794 InstrStage<1, [A9_DRegsN], 0, Required>,
795 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
796 InstrStage<3, [A9_NPipe], 0>,
797 InstrStage<3, [A9_LSUnit]>],
798 [2, 2, 3, 2, 1]>,
799 // VLD1x4u
800 InstrItinData,
801 InstrStage<1, [A9_MUX0], 0>,
802 InstrStage<1, [A9_DRegsN], 0, Required>,
803 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
804 InstrStage<3, [A9_NPipe], 0>,
805 InstrStage<3, [A9_LSUnit]>],
806 [2, 2, 3, 3, 2, 1]>,
807 //
808 // VLD1ln
809 InstrItinData,
810 InstrStage<1, [A9_MUX0], 0>,
811 InstrStage<1, [A9_DRegsN], 0, Required>,
812 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
813 InstrStage<3, [A9_NPipe], 0>,
814 InstrStage<3, [A9_LSUnit]>],
815 [4, 1, 1, 1]>,
816 //
817 // VLD1lnu
818 InstrItinData,
819 InstrStage<1, [A9_MUX0], 0>,
820 InstrStage<1, [A9_DRegsN], 0, Required>,
821 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
822 InstrStage<3, [A9_NPipe], 0>,
823 InstrStage<3, [A9_LSUnit]>],
824 [4, 2, 1, 1, 1, 1]>,
825 //
826 // VLD1dup
827 InstrItinData,
828 InstrStage<1, [A9_MUX0], 0>,
829 InstrStage<1, [A9_DRegsN], 0, Required>,
830 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
831 InstrStage<2, [A9_NPipe], 0>,
832 InstrStage<2, [A9_LSUnit]>],
833 [3, 1]>,
834 //
835 // VLD1dupu
836 InstrItinData,
837 InstrStage<1, [A9_MUX0], 0>,
838 InstrStage<1, [A9_DRegsN], 0, Required>,
839 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
840 InstrStage<2, [A9_NPipe], 0>,
841 InstrStage<2, [A9_LSUnit]>],
842 [3, 2, 1, 1]>,
843 //
844 // VLD2
845 InstrItinData,
846 InstrStage<1, [A9_MUX0], 0>,
847 InstrStage<1, [A9_DRegsN], 0, Required>,
848 // Extra latency cycles since wbck is 7 cycles
849 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
850 InstrStage<2, [A9_NPipe], 0>,
851 InstrStage<2, [A9_LSUnit]>],
852 [3, 3, 1]>,
853 //
854 // VLD2x2
855 InstrItinData,
856 InstrStage<1, [A9_MUX0], 0>,
857 InstrStage<1, [A9_DRegsN], 0, Required>,
858 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
859 InstrStage<3, [A9_NPipe], 0>,
860 InstrStage<3, [A9_LSUnit]>],
861 [3, 4, 3, 4, 1]>,
862 //
863 // VLD2ln
864 InstrItinData,
865 InstrStage<1, [A9_MUX0], 0>,
866 InstrStage<1, [A9_DRegsN], 0, Required>,
867 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
868 InstrStage<3, [A9_NPipe], 0>,
869 InstrStage<3, [A9_LSUnit]>],
870 [4, 4, 1, 1, 1, 1]>,
871 //
872 // VLD2u
873 InstrItinData,
874 InstrStage<1, [A9_MUX0], 0>,
875 InstrStage<1, [A9_DRegsN], 0, Required>,
876 // Extra latency cycles since wbck is 7 cycles
877 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
878 InstrStage<2, [A9_NPipe], 0>,
879 InstrStage<2, [A9_LSUnit]>],
880 [3, 3, 2, 1, 1, 1]>,
881 //
882 // VLD2x2u
883 InstrItinData,
884 InstrStage<1, [A9_MUX0], 0>,
885 InstrStage<1, [A9_DRegsN], 0, Required>,
886 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
887 InstrStage<3, [A9_NPipe], 0>,
888 InstrStage<3, [A9_LSUnit]>],
889 [3, 4, 3, 4, 2, 1]>,
890 //
891 // VLD2lnu
892 InstrItinData,
893 InstrStage<1, [A9_MUX0], 0>,
894 InstrStage<1, [A9_DRegsN], 0, Required>,
895 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
896 InstrStage<3, [A9_NPipe], 0>,
897 InstrStage<3, [A9_LSUnit]>],
898 [4, 4, 2, 1, 1, 1, 1, 1]>,
899 //
900 // VLD2dup
901 InstrItinData,
902 InstrStage<1, [A9_MUX0], 0>,
903 InstrStage<1, [A9_DRegsN], 0, Required>,
904 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
905 InstrStage<2, [A9_NPipe], 0>,
906 InstrStage<2, [A9_LSUnit]>],
907 [3, 3, 1]>,
908 //
909 // VLD2dupu
910 InstrItinData,
911 InstrStage<1, [A9_MUX0], 0>,
912 InstrStage<1, [A9_DRegsN], 0, Required>,
913 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
914 InstrStage<2, [A9_NPipe], 0>,
915 InstrStage<2, [A9_LSUnit]>],
916 [3, 3, 2, 1, 1]>,
917 //
918 // VLD3
919 InstrItinData,
920 InstrStage<1, [A9_MUX0], 0>,
921 InstrStage<1, [A9_DRegsN], 0, Required>,
922 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
923 InstrStage<4, [A9_NPipe], 0>,
924 InstrStage<4, [A9_LSUnit]>],
925 [4, 4, 5, 1]>,
924 [3, 3, 4, 1]>,
926925 //
927926 // VLD3ln
928927 InstrItinData,
937936 InstrItinData,
938937 InstrStage<1, [A9_MUX0], 0>,
939938 InstrStage<1, [A9_DRegsN], 0, Required>,
940 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
941 InstrStage<4, [A9_NPipe], 0>,
942 InstrStage<4, [A9_LSUnit]>],
943 [4, 4, 5, 2, 1]>,
939 InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
940 InstrStage<3, [A9_NPipe], 0>,
941 InstrStage<3, [A9_LSUnit]>],
942 [3, 3, 4, 2, 1]>,
944943 //
945944 // VLD3lnu
946945 InstrItinData,
973972 InstrItinData,
974973 InstrStage<1, [A9_MUX0], 0>,
975974 InstrStage<1, [A9_DRegsN], 0, Required>,
975 InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
976 InstrStage<3, [A9_NPipe], 0>,
977 InstrStage<3, [A9_LSUnit]>],
978 [3, 3, 4, 4, 1]>,
979 //
980 // VLD4ln
981 InstrItinData,
982 InstrStage<1, [A9_MUX0], 0>,
983 InstrStage<1, [A9_DRegsN], 0, Required>,
976984 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
977985 InstrStage<4, [A9_NPipe], 0>,
978986 InstrStage<4, [A9_LSUnit]>],
979 [4, 4, 5, 5, 1]>,
980 //
981 // VLD4ln
982 InstrItinData,
983 InstrStage<1, [A9_MUX0], 0>,
984 InstrStage<1, [A9_DRegsN], 0, Required>,
985 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
986 InstrStage<5, [A9_NPipe], 0>,
987 InstrStage<5, [A9_LSUnit]>],
988 [5, 5, 6, 6, 1, 1, 1, 1, 2, 2]>,
987 [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>,
989988 //
990989 // VLD4u
991990 InstrItinData,
991 InstrStage<1, [A9_MUX0], 0>,
992 InstrStage<1, [A9_DRegsN], 0, Required>,
993 InstrStage<9,[A9_DRegsVFP], 0, Reserved>,
994 InstrStage<3, [A9_NPipe], 0>,
995 InstrStage<3, [A9_LSUnit]>],
996 [3, 3, 4, 4, 2, 1]>,
997 //
998 // VLD4lnu
999 InstrItinData,
9921000 InstrStage<1, [A9_MUX0], 0>,
9931001 InstrStage<1, [A9_DRegsN], 0, Required>,
9941002 InstrStage<10,[A9_DRegsVFP], 0, Reserved>,
9951003 InstrStage<4, [A9_NPipe], 0>,
9961004 InstrStage<4, [A9_LSUnit]>],
997 [4, 4, 5, 5, 2, 1]>,
998 //
999 // VLD4lnu
1000 InstrItinData,
1001 InstrStage<1, [A9_MUX0], 0>,
1002 InstrStage<1, [A9_DRegsN], 0, Required>,
1003 InstrStage<11,[A9_DRegsVFP], 0, Reserved>,
1004 InstrStage<5, [A9_NPipe], 0>,
1005 InstrStage<5, [A9_LSUnit]>],
1006 [5, 5, 6, 6, 2, 1, 1, 1, 1, 1, 2, 2]>,
1005 [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
10071006 //
10081007 // VLD4dup
10091008 InstrItinData,
10101009 InstrStage<1, [A9_MUX0], 0>,
10111010 InstrStage<1, [A9_DRegsN], 0, Required>,
1012 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1011 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1012 InstrStage<2, [A9_NPipe], 0>,
1013 InstrStage<2, [A9_LSUnit]>],
1014 [2, 2, 3, 3, 1]>,
1015 //
1016 // VLD4dupu
1017 InstrItinData,
1018 InstrStage<1, [A9_MUX0], 0>,
1019 InstrStage<1, [A9_DRegsN], 0, Required>,
1020 InstrStage<8, [A9_DRegsVFP], 0, Reserved>,
1021 InstrStage<2, [A9_NPipe], 0>,
1022 InstrStage<2, [A9_LSUnit]>],
1023 [2, 2, 3, 3, 2, 1, 1]>,
1024 //
1025 // VST1
1026 InstrItinData,
1027 InstrStage<1, [A9_MUX0], 0>,
1028 InstrStage<1, [A9_DRegsN], 0, Required>,
1029 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1030 InstrStage<1, [A9_NPipe], 0>,
1031 InstrStage<1, [A9_LSUnit]>],
1032 [1, 1, 1]>,
1033 //
1034 // VST1x2
1035 InstrItinData,
1036 InstrStage<1, [A9_MUX0], 0>,
1037 InstrStage<1, [A9_DRegsN], 0, Required>,
1038 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1039 InstrStage<1, [A9_NPipe], 0>,
1040 InstrStage<1, [A9_LSUnit]>],
1041 [1, 1, 1, 1]>,
1042 //
1043 // VST1x3
1044 InstrItinData,
1045 InstrStage<1, [A9_MUX0], 0>,
1046 InstrStage<1, [A9_DRegsN], 0, Required>,
1047 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1048 InstrStage<2, [A9_NPipe], 0>,
1049 InstrStage<2, [A9_LSUnit]>],
1050 [1, 1, 1, 1, 2]>,
1051 //
1052 // VST1x4
1053 InstrItinData,
1054 InstrStage<1, [A9_MUX0], 0>,
1055 InstrStage<1, [A9_DRegsN], 0, Required>,
1056 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1057 InstrStage<2, [A9_NPipe], 0>,
1058 InstrStage<2, [A9_LSUnit]>],
1059 [1, 1, 1, 1, 2, 2]>,
1060 //
1061 // VST1u
1062 InstrItinData,
1063 InstrStage<1, [A9_MUX0], 0>,
1064 InstrStage<1, [A9_DRegsN], 0, Required>,
1065 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1066 InstrStage<1, [A9_NPipe], 0>,
1067 InstrStage<1, [A9_LSUnit]>],
1068 [2, 1, 1, 1, 1]>,
1069 //
1070 // VST1x2u
1071 InstrItinData,
1072 InstrStage<1, [A9_MUX0], 0>,
1073 InstrStage<1, [A9_DRegsN], 0, Required>,
1074 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1075 InstrStage<1, [A9_NPipe], 0>,
1076 InstrStage<1, [A9_LSUnit]>],
1077 [2, 1, 1, 1, 1, 1]>,
1078 //
1079 // VST1x3u
1080 InstrItinData,
1081 InstrStage<1, [A9_MUX0], 0>,
1082 InstrStage<1, [A9_DRegsN], 0, Required>,
1083 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1084 InstrStage<2, [A9_NPipe], 0>,
1085 InstrStage<2, [A9_LSUnit]>],
1086 [2, 1, 1, 1, 1, 1, 2]>,
1087 //
1088 // VST1x4u
1089 InstrItinData,
1090 InstrStage<1, [A9_MUX0], 0>,
1091 InstrStage<1, [A9_DRegsN], 0, Required>,
1092 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1093 InstrStage<2, [A9_NPipe], 0>,
1094 InstrStage<2, [A9_LSUnit]>],
1095 [2, 1, 1, 1, 1, 1, 2, 2]>,
1096 //
1097 // VST1ln
1098 InstrItinData,
1099 InstrStage<1, [A9_MUX0], 0>,
1100 InstrStage<1, [A9_DRegsN], 0, Required>,
1101 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1102 InstrStage<1, [A9_NPipe], 0>,
1103 InstrStage<1, [A9_LSUnit]>],
1104 [1, 1, 1]>,
1105 //
1106 // VST1lnu
1107 InstrItinData,
1108 InstrStage<1, [A9_MUX0], 0>,
1109 InstrStage<1, [A9_DRegsN], 0, Required>,
1110 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1111 InstrStage<1, [A9_NPipe], 0>,
1112 InstrStage<1, [A9_LSUnit]>],
1113 [2, 1, 1, 1, 1]>,
1114 //
1115 // VST2
1116 InstrItinData,
1117 InstrStage<1, [A9_MUX0], 0>,
1118 InstrStage<1, [A9_DRegsN], 0, Required>,
1119 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1120 InstrStage<1, [A9_NPipe], 0>,
1121 InstrStage<1, [A9_LSUnit]>],
1122 [1, 1, 1, 1]>,
1123 //
1124 // VST2x2
1125 InstrItinData,
1126 InstrStage<1, [A9_MUX0], 0>,
1127 InstrStage<1, [A9_DRegsN], 0, Required>,
1128 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
10131129 InstrStage<3, [A9_NPipe], 0>,
10141130 InstrStage<3, [A9_LSUnit]>],
1015 [3, 3, 4, 4, 1]>,
1016 //
1017 // VLD4dupu
1018 InstrItinData,
1019 InstrStage<1, [A9_MUX0], 0>,
1020 InstrStage<1, [A9_DRegsN], 0, Required>,
1021 InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
1131 [1, 1, 1, 1, 2, 2]>,
1132 //
1133 // VST2u
1134 InstrItinData,
1135 InstrStage<1, [A9_MUX0], 0>,
1136 InstrStage<1, [A9_DRegsN], 0, Required>,
1137 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1138 InstrStage<1, [A9_NPipe], 0>,
1139 InstrStage<1, [A9_LSUnit]>],
1140 [2, 1, 1, 1, 1, 1]>,
1141 //
1142 // VST2x2u
1143 InstrItinData,
1144 InstrStage<1, [A9_MUX0], 0>,
1145 InstrStage<1, [A9_DRegsN], 0, Required>,
1146 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
10221147 InstrStage<3, [A9_NPipe], 0>,
10231148 InstrStage<3, [A9_LSUnit]>],
1024 [3, 3, 4, 4, 2, 1, 1]>,
1025 //
1026 // VST1
1027 InstrItinData>,
1149 [2, 1, 1, 1, 1, 1, 2, 2]>,
1150 //
1151 // VST2ln
1152 InstrItinData,
1153 InstrStage<1, [A9_MUX0], 0>,
1154 InstrStage<1, [A9_DRegsN], 0, Required>,
1155 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1156 InstrStage<1, [A9_NPipe], 0>,
1157 InstrStage<1, [A9_LSUnit]>],
1158 [1, 1, 1, 1]>,
1159 //
1160 // VST2lnu
1161 InstrItinData,
1162 InstrStage<1, [A9_MUX0], 0>,
1163 InstrStage<1, [A9_DRegsN], 0, Required>,
1164 InstrStage<1, [A9_DRegsVFP], 0, Reserved>,
1165 InstrStage<1, [A9_NPipe], 0>,
1166 InstrStage<1, [A9_LSUnit]>],
1167 [2, 1, 1, 1, 1, 1]>,
1168 //
1169 // VST3
1170 InstrItinData,
10281171 InstrStage<1, [A9_MUX0], 0>,
10291172 InstrStage<1, [A9_DRegsN], 0, Required>,
10301173 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
10311174 InstrStage<2, [A9_NPipe], 0>,
10321175 InstrStage<2, [A9_LSUnit]>],
1033 [1, 1, 1]>,
1034 //
1035 // VST1x2
1036 InstrItinData>,
1176 [1, 1, 1, 1, 2]>,
1177 //
1178 // VST3u
1179 InstrItinData,
10371180 InstrStage<1, [A9_MUX0], 0>,
10381181 InstrStage<1, [A9_DRegsN], 0, Required>,
10391182 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
10401183 InstrStage<2, [A9_NPipe], 0>,
10411184 InstrStage<2, [A9_LSUnit]>],
1042 [1, 1, 1, 1]>,
1043 //
1044 // VST1x3
1045 InstrItinData>,
1185 [2, 1, 1, 1, 1, 1, 2]>,
1186 //
1187 // VST3ln
1188 InstrItinData,
10461189 InstrStage<1, [A9_MUX0], 0>,
10471190 InstrStage<1, [A9_DRegsN], 0, Required>,
10481191 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
10501193 InstrStage<3, [A9_LSUnit]>],
10511194 [1, 1, 1, 1, 2]>,
10521195 //
1053 // VST1x4
1054 InstrItinData,
1055 InstrStage<1, [A9_MUX0], 0>,
1056 InstrStage<1, [A9_DRegsN], 0, Required>,
1057 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1058 InstrStage<3, [A9_NPipe], 0>,
1059 InstrStage<3, [A9_LSUnit]>],
1060 [1, 1, 1, 1, 2, 2]>,
1061 //
1062 // VST1u
1063 InstrItinData,
1064 InstrStage<1, [A9_MUX0], 0>,
1065 InstrStage<1, [A9_DRegsN], 0, Required>,
1066 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1067 InstrStage<2, [A9_NPipe], 0>,
1068 InstrStage<2, [A9_LSUnit]>],
1069 [2, 1, 1, 1, 1]>,
1070 //
1071 // VST1x2u
1072 InstrItinData,
1073 InstrStage<1, [A9_MUX0], 0>,
1074 InstrStage<1, [A9_DRegsN], 0, Required>,
1075 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1076 InstrStage<2, [A9_NPipe], 0>,
1077 InstrStage<2, [A9_LSUnit]>],
1078 [2, 1, 1, 1, 1, 1]>,
1079 //
1080 // VST1x3u
1081 InstrItinData,
1082 InstrStage<1, [A9_MUX0], 0>,
1083 InstrStage<1, [A9_DRegsN], 0, Required>,
1084 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1085 InstrStage<3, [A9_NPipe], 0>,
1086 InstrStage<3, [A9_LSUnit]>],
1087 [2, 1, 1, 1, 1, 1, 2]>,
1088 //
1089 // VST1x4u
1090 InstrItinData,
1091 InstrStage<1, [A9_MUX0], 0>,
1092 InstrStage<1, [A9_DRegsN], 0, Required>,
1093 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1094 InstrStage<3, [A9_NPipe], 0>,
1095 InstrStage<3, [A9_LSUnit]>],
1096 [2, 1, 1, 1, 1, 1, 2, 2]>,
1097 //
1098 // VST1ln
1099 InstrItinData,
1100 InstrStage<1, [A9_MUX0], 0>,
1101 InstrStage<1, [A9_DRegsN], 0, Required>,
1102 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1103 InstrStage<2, [A9_NPipe], 0>,
1104 InstrStage<2, [A9_LSUnit]>],
1105 [1, 1, 1]>,
1106 //
1107 // VST1lnu
1108 InstrItinData,
1109 InstrStage<1, [A9_MUX0], 0>,
1110 InstrStage<1, [A9_DRegsN], 0, Required>,
1111 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1112 InstrStage<3, [A9_NPipe], 0>,
1113 InstrStage<3, [A9_LSUnit]>],
1114 [2, 1, 1, 1, 1]>,
1115 //
1116 // VST2
1117 InstrItinData,
1118 InstrStage<1, [A9_MUX0], 0>,
1119 InstrStage<1, [A9_DRegsN], 0, Required>,
1120 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1121 InstrStage<2, [A9_NPipe], 0>,
1122 InstrStage<2, [A9_LSUnit]>],
1123 [1, 1, 1, 1]>,
1124 //
1125 // VST2x2
1126 InstrItinData,
1127 InstrStage<1, [A9_MUX0], 0>,
1128 InstrStage<1, [A9_DRegsN], 0, Required>,
1129 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1130 InstrStage<3, [A9_NPipe], 0>,
1131 InstrStage<3, [A9_LSUnit]>],
1132 [1, 1, 1, 1, 2, 2]>,
1133 //
1134 // VST2u
1135 InstrItinData,
1136 InstrStage<1, [A9_MUX0], 0>,
1137 InstrStage<1, [A9_DRegsN], 0, Required>,
1138 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1139 InstrStage<2, [A9_NPipe], 0>,
1140 InstrStage<2, [A9_LSUnit]>],
1141 [2, 1, 1, 1, 1, 1]>,
1142 //
1143 // VST2x2u
1144 InstrItinData,
1145 InstrStage<1, [A9_MUX0], 0>,
1146 InstrStage<1, [A9_DRegsN], 0, Required>,
1147 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1148 InstrStage<3, [A9_NPipe], 0>,
1149 InstrStage<3, [A9_LSUnit]>],
1150 [2, 1, 1, 1, 1, 1, 2, 2]>,
1151 //
1152 // VST2ln
1153 InstrItinData,
1154 InstrStage<1, [A9_MUX0], 0>,
1155 InstrStage<1, [A9_DRegsN], 0, Required>,
1156 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1157 InstrStage<2, [A9_NPipe], 0>,
1158 InstrStage<2, [A9_LSUnit]>],
1159 [1, 1, 1, 1]>,
1160 //
1161 // VST2lnu
1162 InstrItinData,
1163 InstrStage<1, [A9_MUX0], 0>,
1164 InstrStage<1, [A9_DRegsN], 0, Required>,
1165 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1166 InstrStage<3, [A9_NPipe], 0>,
1167 InstrStage<3, [A9_LSUnit]>],
1168 [2, 1, 1, 1, 1, 1]>,
1169 //
1170 // VST3
1171 InstrItinData,
1172 InstrStage<1, [A9_MUX0], 0>,
1173 InstrStage<1, [A9_DRegsN], 0, Required>,
1174 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1175 InstrStage<3, [A9_NPipe], 0>,
1176 InstrStage<3, [A9_LSUnit]>],
1177 [1, 1, 1, 1, 2]>,
1178 //
1179 // VST3u
1180 InstrItinData,
1196 // VST3lnu
1197 InstrItinData,
11811198 InstrStage<1, [A9_MUX0], 0>,
11821199 InstrStage<1, [A9_DRegsN], 0, Required>,
11831200 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
11851202 InstrStage<3, [A9_LSUnit]>],
11861203 [2, 1, 1, 1, 1, 1, 2]>,
11871204 //
1188 // VST3ln
1189 InstrItinData,
1190 InstrStage<1, [A9_MUX0], 0>,
1191 InstrStage<1, [A9_DRegsN], 0, Required>,
1192 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1193 InstrStage<3, [A9_NPipe], 0>,
1194 InstrStage<3, [A9_LSUnit]>],
1195 [1, 1, 1, 1, 2]>,
1196 //
1197 // VST3lnu
1198 InstrItinData,
1199 InstrStage<1, [A9_MUX0], 0>,
1200 InstrStage<1, [A9_DRegsN], 0, Required>,
1201 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1202 InstrStage<3, [A9_NPipe], 0>,
1203 InstrStage<3, [A9_LSUnit]>],
1204 [2, 1, 1, 1, 1, 1, 2]>,
1205 //
12061205 // VST4
12071206 InstrItinData,
12081207 InstrStage<1, [A9_MUX0], 0>,
12091208 InstrStage<1, [A9_DRegsN], 0, Required>,
1210 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1211 InstrStage<3, [A9_NPipe], 0>,
1212 InstrStage<3, [A9_LSUnit]>],
1209 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1210 InstrStage<2, [A9_NPipe], 0>,
1211 InstrStage<2, [A9_LSUnit]>],
12131212 [1, 1, 1, 1, 2, 2]>,
12141213 //
12151214 // VST4u
12161215 InstrItinData,
12171216 InstrStage<1, [A9_MUX0], 0>,
12181217 InstrStage<1, [A9_DRegsN], 0, Required>,
1219 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1220 InstrStage<3, [A9_NPipe], 0>,
1221 InstrStage<3, [A9_LSUnit]>],
1218 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1219 InstrStage<2, [A9_NPipe], 0>,
1220 InstrStage<2, [A9_LSUnit]>],
12221221 [2, 1, 1, 1, 1, 1, 2, 2]>,
12231222 //
12241223 // VST4ln
12251224 InstrItinData,
12261225 InstrStage<1, [A9_MUX0], 0>,
12271226 InstrStage<1, [A9_DRegsN], 0, Required>,
1228 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1229 InstrStage<3, [A9_NPipe], 0>,
1230 InstrStage<3, [A9_LSUnit]>],
1227 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1228 InstrStage<2, [A9_NPipe], 0>,
1229 InstrStage<2, [A9_LSUnit]>],
12311230 [1, 1, 1, 1, 2, 2]>,
12321231 //
12331232 // VST4lnu
12341233 InstrItinData,
12351234 InstrStage<1, [A9_MUX0], 0>,
12361235 InstrStage<1, [A9_DRegsN], 0, Required>,
1237 InstrStage<3, [A9_DRegsVFP], 0, Reserved>,
1238 InstrStage<3, [A9_NPipe], 0>,
1239 InstrStage<3, [A9_LSUnit]>],
1236 InstrStage<2, [A9_DRegsVFP], 0, Reserved>,
1237 InstrStage<2, [A9_NPipe], 0>,
1238 InstrStage<2, [A9_LSUnit]>],
12401239 [2, 1, 1, 1, 1, 1, 2, 2]>,
12411240
12421241 //