llvm.org GIT mirror llvm / 75a1426
Merge 81814 from mainline. On x86-64, the 32-bit cmov doesn't actually clear the high 32-bit of its result if the condition is false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81977 91177308-0d34-0410-b5e6-96231b3b80d8 Tanya Lattner 10 years ago
2 changed file(s) with 24 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
362362 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
363363
364364 // Any instruction that defines a 32-bit result leaves the high half of the
365 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
366 // be copying from a truncate, but any other 32-bit operation will zero-extend
365 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
366 // be copying from a truncate. And x86's cmov doesn't do anything if the
367 // condition is false. But any other 32-bit operation will zero-extend
367368 // up to 64 bits.
368369 def def32 : PatLeaf<(i32 GR32:$src), [{
369370 return N->getOpcode() != ISD::TRUNCATE &&
370371 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
371 N->getOpcode() != ISD::CopyFromReg;
372 N->getOpcode() != ISD::CopyFromReg &&
373 N->getOpcode() != X86ISD::CMOV;
372374 }]>;
373375
374376 // In the case of a 32-bit def that is known to implicitly zero-extend,
0 ; RUN: llc < %s -march=x86-64 | FileCheck %s
1
2 ; x86's 32-bit cmov doesn't clobber the high 32 bits of the destination
3 ; if the condition is false. An explicit zero-extend (movl) is needed
4 ; after the cmov.
5
6 ; CHECK: cmovne %edi, %esi
7 ; CHECK-NEXT: movl %esi, %edi
8
9 declare void @bar(i64) nounwind
10
11 define void @foo(i64 %a, i64 %b, i1 %p) nounwind {
12 %c = trunc i64 %a to i32
13 %d = trunc i64 %b to i32
14 %e = select i1 %p, i32 %c, i32 %d
15 %f = zext i32 %e to i64
16 call void @bar(i64 %f)
17 ret void
18 }