llvm.org GIT mirror llvm / 7597212
Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 9 years ago
15 changed file(s) with 248 addition(s) and 90 deletion(s). Raw diff Collapse all Expand all
154154 VK_TPOFF,
155155 VK_DTPOFF,
156156 VK_TLVP, // Mach-O thread local variable relocation
157 VK_ARM_HI16, // The R_ARM_MOVT_ABS relocation (:upper16: in the .s file)
158 VK_ARM_LO16, // The R_ARM_MOVW_ABS_NC relocation (:lower16: in the .w file)
159157 // FIXME: We'd really like to use the generic Kinds listed above for these.
160158 VK_ARM_PLT, // ARM-style PLT references. i.e., (PLT) instead of @PLT
161159 VK_ARM_TLSGD, // ditto for TLSGD, GOT, GOTOFF, TPOFF and GOTTPOFF
420418 virtual void PrintImpl(raw_ostream &OS) const = 0;
421419 virtual bool EvaluateAsRelocatableImpl(MCValue &Res,
422420 const MCAsmLayout *Layout) const = 0;
423
421 virtual void AddValueSymbols(MCAssembler *) const = 0;
424422
425423 static bool classof(const MCExpr *E) {
426424 return E->getKind() == MCExpr::Target;
4141 // absolute names.
4242 bool UseParens = Sym.getName()[0] == '$';
4343
44 if (SRE.getKind() == MCSymbolRefExpr::VK_ARM_HI16 ||
45 SRE.getKind() == MCSymbolRefExpr::VK_ARM_LO16)
46 OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind());
47
4844 if (SRE.getKind() == MCSymbolRefExpr::VK_PPC_HA16 ||
4945 SRE.getKind() == MCSymbolRefExpr::VK_PPC_LO16) {
5046 OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind());
6460 SRE.getKind() == MCSymbolRefExpr::VK_ARM_GOTTPOFF)
6561 OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind());
6662 else if (SRE.getKind() != MCSymbolRefExpr::VK_None &&
67 SRE.getKind() != MCSymbolRefExpr::VK_ARM_HI16 &&
68 SRE.getKind() != MCSymbolRefExpr::VK_ARM_LO16 &&
6963 SRE.getKind() != MCSymbolRefExpr::VK_PPC_HA16 &&
7064 SRE.getKind() != MCSymbolRefExpr::VK_PPC_LO16)
7165 OS << '@' << MCSymbolRefExpr::getVariantKindName(SRE.getKind());
195189 case VK_TPOFF: return "TPOFF";
196190 case VK_DTPOFF: return "DTPOFF";
197191 case VK_TLVP: return "TLVP";
198 case VK_ARM_HI16: return ":upper16:";
199 case VK_ARM_LO16: return ":lower16:";
200192 case VK_ARM_PLT: return "(PLT)";
201193 case VK_ARM_GOT: return "(GOT)";
202194 case VK_ARM_GOTOFF: return "(GOTOFF)";
5555
5656 const MCExpr *MCObjectStreamer::AddValueSymbols(const MCExpr *Value) {
5757 switch (Value->getKind()) {
58 case MCExpr::Target: llvm_unreachable("Can't handle target exprs yet!");
58 case MCExpr::Target:
59 cast(Value)->AddValueSymbols(Assembler);
60 break;
61
5962 case MCExpr::Constant:
6063 break;
6164
250250 return Binary;
251251 }
252252
253 unsigned getMovtImmOpValue(const MachineInstr &MI, unsigned Op) const {
253 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const {
254254 return 0;
255255 }
256256
424424 let EncoderMethod = "getImmMinusOneOpValue";
425425 }
426426
427 // For movt/movw - sets the MC Encoder method.
427 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
428428 // The imm is split into imm{15-12}, imm{11-0}
429429 //
430 def movt_imm : Operand {
431 let EncoderMethod = "getMovtImmOpValue";
430 def i32imm_hilo16 : Operand {
431 let EncoderMethod = "getHiLo16ImmOpValue";
432432 }
433433
434434 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
19061906 }
19071907
19081908 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1909 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins movt_imm:$imm),
1909 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
19101910 DPFrm, IIC_iMOVi,
19111911 "movw", "\t$Rd, $imm",
19121912 [(set GPR:$Rd, imm0_65535:$imm)]>,
19211921 }
19221922
19231923 let Constraints = "$src = $Rd" in
1924 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, movt_imm:$imm),
1924 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
19251925 DPFrm, IIC_iMOVi,
19261926 "movt", "\t$Rd, $imm",
19271927 [(set GPR:$Rd,
30493049 }
30503050
30513051 let isMoveImm = 1 in
3052 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, movt_imm:$imm),
3052 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm_hilo16:$imm),
30533053 DPFrm, IIC_iMOVi,
30543054 "movw", "\t$Rd, $imm",
30553055 []>,
16761676 }
16771677
16781678 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1679 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm:$imm), IIC_iMOVi,
1679 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm_hilo16:$imm), IIC_iMOVi,
16801680 "movw", "\t$Rd, $imm",
16811681 [(set rGPR:$Rd, imm0_65535:$imm)]> {
16821682 let Inst{31-27} = 0b11110;
16961696 }
16971697
16981698 let Constraints = "$src = $Rd" in
1699 def t2MOVTi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
1699 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1700 (ins rGPR:$src, i32imm_hilo16:$imm), IIC_iMOVi,
17001701 "movt", "\t$Rd, $imm",
17011702 [(set rGPR:$Rd,
17021703 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
26832684 }
26842685
26852686 let isMoveImm = 1 in
2686 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm:$imm),
2687 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm_hilo16:$imm),
26872688 IIC_iCMOVi,
26882689 "movw", "\t$Rd, $imm", []>,
26892690 RegConstraint<"$false = $Rd"> {
1515 #include "ARMAddressingModes.h"
1616 #include "ARMFixupKinds.h"
1717 #include "ARMInstrInfo.h"
18 #include "ARMMCExpr.h"
1819 #include "llvm/MC/MCCodeEmitter.h"
1920 #include "llvm/MC/MCExpr.h"
2021 #include "llvm/MC/MCInst.h"
5253 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
5354 SmallVectorImpl &Fixups) const;
5455
55 /// getMovtImmOpValue - Return the encoding for the movw/movt pair
56 uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
57 SmallVectorImpl &Fixups) const;
56 /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
57 /// the specified operand. This is used for operands with :lower16: and
58 /// :upper16: prefixes.
59 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
60 SmallVectorImpl &Fixups) const;
5861
5962 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
6063 unsigned &Reg, unsigned &Imm,
625628 return Binary;
626629 }
627630
628 // FIXME: This routine needs to handle more MCExpr types
629 static const MCSymbolRefExpr *FindLHSymExpr(const MCExpr *E) {
630 // recurse left child until finding a MCSymbolRefExpr
631 switch (E->getKind()) {
632 case MCExpr::SymbolRef:
633 return cast(E);
634 case MCExpr::Binary:
635 return FindLHSymExpr(cast(E)->getLHS());
636 default:
637 return NULL;
638 }
639 }
640
641631 // FIXME: This routine assumes that a binary
642632 // expression will always result in a PCRel expression
643633 // In reality, its only true if one or more subexpressions
651641 }
652642 }
653643
654 uint32_t ARMMCCodeEmitter::
655 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
656 SmallVectorImpl &Fixups) const {
644 uint32_t
645 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
646 SmallVectorImpl &Fixups) const {
657647 // {20-16} = imm{15-12}
658648 // {11-0} = imm{11-0}
659649 const MCOperand &MO = MI.getOperand(OpIdx);
660 if (MO.isImm()) {
650 if (MO.isImm())
651 // Hi / lo 16 bits already extracted during earlier passes.
661652 return static_cast(MO.getImm());
662 } else if (const MCSymbolRefExpr *Expr =
663 FindLHSymExpr(MO.getExpr())) {
664 // FIXME: :lower16: and :upper16: should be applicable to
665 // to whole expression, not just symbolrefs
666 // Until that change takes place, this hack is required to
667 // generate working code.
668 const MCExpr *OrigExpr = MO.getExpr();
653
654 // Handle :upper16: and :lower16: assembly prefixes.
655 const MCExpr *E = MO.getExpr();
656 if (E->getKind() == MCExpr::Target) {
657 const ARMMCExpr *ARM16Expr = cast(E);
658 E = ARM16Expr->getSubExpr();
659
669660 MCFixupKind Kind;
670 switch (Expr->getKind()) {
661 switch (ARM16Expr->getKind()) {
671662 default: assert(0 && "Unsupported ARMFixup");
672 case MCSymbolRefExpr::VK_ARM_HI16:
663 case ARMMCExpr::VK_ARM_HI16:
673664 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
674 if (EvaluateAsPCRel(OrigExpr))
665 if (EvaluateAsPCRel(E))
675666 Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel);
676667 break;
677 case MCSymbolRefExpr::VK_ARM_LO16:
668 case ARMMCExpr::VK_ARM_LO16:
678669 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
679 if (EvaluateAsPCRel(OrigExpr))
670 if (EvaluateAsPCRel(E))
680671 Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel);
681672 break;
682673 }
683 Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind));
674 Fixups.push_back(MCFixup::Create(0, E, Kind));
684675 return 0;
685676 };
677
686678 llvm_unreachable("Unsupported MCExpr type in MCOperand!");
687679 return 0;
688680 }
11721164 case ARMII::Size4Bytes: Size = 4; break;
11731165 }
11741166 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups);
1175 // Thumb 32-bit wide instructions need to be have the high order halfword
1176 // emitted first.
1167 // Thumb 32-bit wide instructions need to emit the high order halfword
1168 // first.
11771169 if (Subtarget.isThumb() && Size == 4) {
11781170 EmitConstant(Binary >> 16, 2, OS);
11791171 EmitConstant(Binary & 0xffff, 2, OS);
0 //===-- ARMMCExpr.cpp - ARM specific MC expression classes ----------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #define DEBUG_TYPE "armmcexpr"
10 #include "ARMMCExpr.h"
11 #include "llvm/MC/MCContext.h"
12 #include "llvm/MC/MCAssembler.h"
13 using namespace llvm;
14
15 const ARMMCExpr*
16 ARMMCExpr::Create(VariantKind Kind, const MCExpr *Expr,
17 MCContext &Ctx) {
18 return new (Ctx) ARMMCExpr(Kind, Expr);
19 }
20
21 void ARMMCExpr::PrintImpl(raw_ostream &OS) const {
22 switch (Kind) {
23 default: assert(0 && "Invalid kind!");
24 case VK_ARM_HI16: OS << ":upper16:"; break;
25 case VK_ARM_LO16: OS << ":lower16:"; break;
26 }
27
28 const MCExpr *Expr = getSubExpr();
29 if (Expr->getKind() != MCExpr::SymbolRef)
30 OS << '(';
31 Expr->print(OS);
32 if (Expr->getKind() != MCExpr::SymbolRef)
33 OS << ')';
34 }
35
36 bool
37 ARMMCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
38 const MCAsmLayout *Layout) const {
39 return false;
40 }
41
42 // FIXME: This basically copies MCObjectStreamer::AddValueSymbols. Perhaps
43 // that method should be made public?
44 static void AddValueSymbols_(const MCExpr *Value, MCAssembler *Asm) {
45 switch (Value->getKind()) {
46 case MCExpr::Target:
47 assert(0 && "Can't handle nested target expr!");
48 break;
49
50 case MCExpr::Constant:
51 break;
52
53 case MCExpr::Binary: {
54 const MCBinaryExpr *BE = cast(Value);
55 AddValueSymbols_(BE->getLHS(), Asm);
56 AddValueSymbols_(BE->getRHS(), Asm);
57 break;
58 }
59
60 case MCExpr::SymbolRef:
61 Asm->getOrCreateSymbolData(cast(Value)->getSymbol());
62 break;
63
64 case MCExpr::Unary:
65 AddValueSymbols_(cast(Value)->getSubExpr(), Asm);
66 break;
67 }
68 }
69
70 void ARMMCExpr::AddValueSymbols(MCAssembler *Asm) const {
71 AddValueSymbols_(getSubExpr(), Asm);
72 }
0 //===-- ARMMCExpr.h - ARM specific MC expression classes ------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #ifndef ARMMCEXPR_H
10 #define ARMMCEXPR_H
11
12 #include "llvm/MC/MCExpr.h"
13
14 namespace llvm {
15
16 class ARMMCExpr : public MCTargetExpr {
17 public:
18 enum VariantKind {
19 VK_ARM_None,
20 VK_ARM_HI16, // The R_ARM_MOVT_ABS relocation (:upper16: in the .s file)
21 VK_ARM_LO16 // The R_ARM_MOVW_ABS_NC relocation (:lower16: in the .s file)
22 };
23
24 private:
25 const VariantKind Kind;
26 const MCExpr *Expr;
27
28 explicit ARMMCExpr(VariantKind _Kind, const MCExpr *_Expr)
29 : Kind(_Kind), Expr(_Expr) {}
30
31 public:
32 /// @name Construction
33 /// @{
34
35 static const ARMMCExpr *Create(VariantKind Kind, const MCExpr *Expr,
36 MCContext &Ctx);
37
38 static const ARMMCExpr *CreateUpper16(const MCExpr *Expr, MCContext &Ctx) {
39 return Create(VK_ARM_HI16, Expr, Ctx);
40 }
41
42 static const ARMMCExpr *CreateLower16(const MCExpr *Expr, MCContext &Ctx) {
43 return Create(VK_ARM_LO16, Expr, Ctx);
44 }
45
46 /// @}
47 /// @name Accessors
48 /// @{
49
50 /// getOpcode - Get the kind of this expression.
51 VariantKind getKind() const { return Kind; }
52
53 /// getSubExpr - Get the child of this expression.
54 const MCExpr *getSubExpr() const { return Expr; }
55
56 /// @}
57
58 void PrintImpl(raw_ostream &OS) const;
59 bool EvaluateAsRelocatableImpl(MCValue &Res,
60 const MCAsmLayout *Layout) const;
61 void AddValueSymbols(MCAssembler *) const;
62
63 static bool classof(const MCExpr *E) {
64 return E->getKind() == MCExpr::Target;
65 }
66
67 static bool classof(const ARMMCExpr *) { return true; }
68
69 };
70 } // end namespace llvm
71
72 #endif
1313
1414 #include "ARM.h"
1515 #include "ARMAsmPrinter.h"
16 #include "ARMMCExpr.h"
1617 #include "llvm/Constants.h"
1718 #include "llvm/CodeGen/MachineBasicBlock.h"
1819 #include "llvm/MC/MCExpr.h"
2627 MCContext &Ctx = Printer.OutContext;
2728 const MCExpr *Expr;
2829 switch (MO.getTargetFlags()) {
29 default: assert(0 && "Unknown target flag on symbol operand");
30 case 0:
30 default: {
3131 Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx);
32 switch (MO.getTargetFlags()) {
33 default:
34 assert(0 && "Unknown target flag on symbol operand");
35 case 0:
36 break;
37 case ARMII::MO_LO16:
38 Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx);
39 Expr = ARMMCExpr::CreateLower16(Expr, Ctx);
40 break;
41 case ARMII::MO_HI16:
42 Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx);
43 Expr = ARMMCExpr::CreateUpper16(Expr, Ctx);
44 break;
45 }
3246 break;
33 case ARMII::MO_LO16:
34 Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_LO16, Ctx);
35 break;
36 case ARMII::MO_HI16:
37 Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_HI16, Ctx);
38 break;
47 }
48
3949 case ARMII::MO_PLT:
4050 Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_PLT, Ctx);
4151 break;
88
99 #include "ARM.h"
1010 #include "ARMAddressingModes.h"
11 #include "ARMMCExpr.h"
1112 #include "ARMBaseRegisterInfo.h"
1213 #include "ARMSubtarget.h"
1314 #include "llvm/MC/MCParser/MCAsmLexer.h"
5455 bool ParseRegisterList(SmallVectorImpl &);
5556 bool ParseMemory(SmallVectorImpl &);
5657 bool ParseOperand(SmallVectorImpl &);
57 bool ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind);
58 bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
5859 const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
5960 MCSymbolRefExpr::VariantKind Variant);
6061
869870 return false;
870871 case AsmToken::Colon: {
871872 // ":lower16:" and ":upper16:" expression prefixes
872 MCSymbolRefExpr::VariantKind RefKind;
873 // FIXME: Check it's an expression prefix,
874 // e.g. (FOO - :lower16:BAR) isn't legal.
875 ARMMCExpr::VariantKind RefKind;
873876 if (ParsePrefix(RefKind))
874877 return true;
875878
876 const MCExpr *ExprVal;
877 if (getParser().ParseExpression(ExprVal))
879 const MCExpr *SubExprVal;
880 if (getParser().ParseExpression(SubExprVal))
878881 return true;
879882
880 // TODO: Attach the prefix to the entire expression
881 // instead of just the first symbol.
882 const MCExpr *ModExprVal = ApplyPrefixToExpr(ExprVal, RefKind);
883 if (!ModExprVal) {
884 return TokError("invalid modifier '" + getTok().getIdentifier() +
885 "' (no symbols present)");
886 }
887
883 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
884 getContext());
888885 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
889 Operands.push_back(ARMOperand::CreateImm(ModExprVal, S, E));
886 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
890887 return false;
891888 }
892889 }
893890 }
894891
895 // FIXME: The next 2 routines are hacks to get ARMAsmParser to understand
896 // :lower16: and :upper16:
897 // It still attaches VK_ARM_HI/LO16 to MCSymbolRefExpr, but it really
898 // should be attached to the entire MCExpr as a whole - perhaps using
899 // MCTargetExpr?
900 bool ARMAsmParser::ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind) {
901 RefKind = MCSymbolRefExpr::VK_None;
892 // ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
893 // :lower16: and :upper16:.
894 bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) {
895 RefKind = ARMMCExpr::VK_ARM_None;
902896
903897 // :lower16: and :upper16: modifiers
904898 assert(getLexer().is(AsmToken::Colon) && "expected a :");
911905
912906 StringRef IDVal = Parser.getTok().getIdentifier();
913907 if (IDVal == "lower16") {
914 RefKind = MCSymbolRefExpr::VK_ARM_LO16;
908 RefKind = ARMMCExpr::VK_ARM_LO16;
915909 } else if (IDVal == "upper16") {
916 RefKind = MCSymbolRefExpr::VK_ARM_HI16;
910 RefKind = ARMMCExpr::VK_ARM_HI16;
917911 } else {
918912 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
919913 return true;
3434 ARMInstrInfo.cpp
3535 ARMJITInfo.cpp
3636 ARMMCCodeEmitter.cpp
37 ARMMCExpr.cpp
3738 ARMLoadStoreOptimizer.cpp
3839 ARMMCAsmInfo.cpp
3940 ARMMCInstLower.cpp
1010 movw r0, :lower16:GOT-(.LPC0_2+8)
1111 movt r0, :upper16:GOT-(.LPC0_2+16)
1212 .LPC0_2:
13 @ ASM: movw r0, :lower16:GOT-(.LPC0_2+8)
14 @ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16)
13 @ ASM: movw r0, :lower16:(GOT-(.LPC0_2+8))
14 @ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+16))
1515
1616 @@ make sure that the text section fixups are sane too
1717 @ OBJ: '.text'
0 @ RUN: llvm-mc %s -triple armv7-apple-darwin -show-encoding | FileCheck %s
1
2 _t:
3 movw r0, :lower16:(L_foo$non_lazy_ptr - (L1 + 8))
4 movt r0, :upper16:(L_foo$non_lazy_ptr - (L1 + 8))
5 L1:
6
7 @ CHECK: movw r0, :lower16:(L_foo$non_lazy_ptr-(L1+8)) @ encoding: [A,A,0x00,0xe3]
8 @ CHECK: @ fixup A - offset: 0, value: L_foo$non_lazy_ptr-(L1+8), kind: fixup_arm_movw_lo16_pcrel
9 @ CHECK: movt r0, :upper16:(L_foo$non_lazy_ptr-(L1+8)) @ encoding: [A,A,0x40,0xe3]
10 @ CHECK: @ fixup A - offset: 0, value: L_foo$non_lazy_ptr-(L1+8), kind: fixup_arm_movt_hi16_pcrel
11
12 .comm _foo,4,2
13
14 .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers
15 .align 2
16 L_foo$non_lazy_ptr:
17 .indirect_symbol _foo
18 .long 0
19
20 .subsections_via_symbols
563563 REG("QQQQPR");
564564
565565 IMM("i32imm");
566 IMM("movt_imm");
566 IMM("i32imm_hilo16");
567567 IMM("bf_inv_mask_imm");
568568 IMM("jtblock_operand");
569569 IMM("nohash_imm");