llvm.org GIT mirror llvm / 7581bfa
Get rid of the non-DebugLoc-ified getNOT() method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63442 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 10 years ago
6 changed file(s) with 15 addition(s) and 29 deletion(s). Raw diff Collapse all Expand all
378378 SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy);
379379
380380 /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
381 SDValue getNOT(SDValue Val, MVT VT);
382381 SDValue getNOT(DebugLoc DL, SDValue Val, MVT VT);
383382
384383 /// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
28442844 }
28452845 // fold (select C, 0, X) -> (and (not C), X)
28462846 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2847 SDValue NOTNode = DAG.getNOT(N0, VT);
2847 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
28482848 AddToWorkList(NOTNode.getNode());
2849 return DAG.getNode(ISD::AND, VT, NOTNode, N2);
2849 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
28502850 }
28512851 // fold (select C, X, 1) -> (or (not C), X)
28522852 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
28532853 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
28542854 AddToWorkList(NOTNode.getNode());
2855 return DAG.getNode(ISD::OR, VT, NOTNode, N1);
2855 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
28562856 }
28572857 // fold (select C, X, 0) -> (and C, X)
28582858 if (VT == MVT::i1 && N2C && N2C->isNullValue())
57385738 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
57395739 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
57405740 N0);
5741 SDValue NotN0 = DAG.getNOT(N0, XType);
5741 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
57425742 return DAG.getNode(ISD::SRL, XType,
57435743 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
57445744 DAG.getConstant(XType.getSizeInBits()-1,
63206320 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
63216321 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
63226322 }
6323 Op = DAG.getNOT(Op, VT);
6323 Op = DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT);
63246324 return DAG.getNode(ISD::CTPOP, VT, Op);
63256325 }
63266326 case ISD::CTTZ: {
63296329 // { return 32 - nlz(~x & (x-1)); }
63306330 // see also http://www.hackersdelight.org/HDcode/ntz.cc
63316331 MVT VT = Op.getValueType();
6332 SDValue Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNOT(Op, VT),
6333 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
6332 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
6333 DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT),
6334 DAG.getNode(ISD::SUB, VT, Op,
6335 DAG.getConstant(1, VT)));
63346336 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
63356337 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
63366338 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
836836 VT.getSizeInBits());
837837 return getNode(ISD::AND, DL, Op.getValueType(), Op,
838838 getConstant(Imm, Op.getValueType()));
839 }
840
841 /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
842 ///
843 SDValue SelectionDAG::getNOT(SDValue Val, MVT VT) {
844 SDValue NegOne;
845 if (VT.isVector()) {
846 MVT EltVT = VT.getVectorElementType();
847 SDValue NegOneElt = getConstant(EltVT.getIntegerVTBitMask(), EltVT);
848 std::vector NegOnes(VT.getVectorNumElements(), NegOneElt);
849 NegOne = getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0], NegOnes.size());
850 } else
851 NegOne = getConstant(VT.getIntegerVTBitMask(), VT);
852
853 return getNode(ISD::XOR, VT, Val, NegOne);
854839 }
855840
856841 /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
18401840 default: assert(0 && "Unknown integer setcc!");
18411841 case ISD::SETEQ: // X == Y -> ~(X^Y)
18421842 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1843 N0 = DAG.getNOT(Temp, MVT::i1);
1843 N0 = DAG.getNOT(DebugLoc::getUnknownLoc(), Temp, MVT::i1);
18441844 if (!DCI.isCalledByLegalizer())
18451845 DCI.AddToWorklist(Temp.getNode());
18461846 break;
18491849 break;
18501850 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
18511851 case ISD::SETULT: // X X == 0 & Y == 1 --> ~X & Y
1852 Temp = DAG.getNOT(N0, MVT::i1);
1852 Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1);
18531853 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
18541854 if (!DCI.isCalledByLegalizer())
18551855 DCI.AddToWorklist(Temp.getNode());
18561856 break;
18571857 case ISD::SETLT: // X X == 1 & Y == 0 --> ~Y & X
18581858 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1859 Temp = DAG.getNOT(N1, MVT::i1);
1859 Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1);
18601860 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
18611861 if (!DCI.isCalledByLegalizer())
18621862 DCI.AddToWorklist(Temp.getNode());
18631863 break;
18641864 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
18651865 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1866 Temp = DAG.getNOT(N0, MVT::i1);
1866 Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1);
18671867 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
18681868 if (!DCI.isCalledByLegalizer())
18691869 DCI.AddToWorklist(Temp.getNode());
18701870 break;
18711871 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
18721872 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1873 Temp = DAG.getNOT(N1, MVT::i1);
1873 Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1);
18741874 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
18751875 break;
18761876 }
52795279
52805280 // If the logical-not of the result is required, perform that now.
52815281 if (Invert)
5282 Result = DAG.getNOT(Result, VT);
5282 Result = DAG.getNOT(Op.getDebugLoc(), Result, VT);
52835283
52845284 return Result;
52855285 }