llvm.org GIT mirror llvm / 756d2cc
Remove an unused argument. The MCInst opcode is set in the ConvertToMCInst() function nowadays. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163030 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 7 years ago
2 changed file(s) with 43 addition(s) and 48 deletion(s). Raw diff Collapse all Expand all
180180 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
181181
182182 // Asm Match Converter Methods
183 void cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
184 const SmallVectorImpl &);
185 void cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
186 const SmallVectorImpl &);
187 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
183 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl &);
184 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl &);
185 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
188186 const SmallVectorImpl &);
189 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
187 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
190188 const SmallVectorImpl &);
191 void cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
189 void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
192190 const SmallVectorImpl &);
193 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
191 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
194192 const SmallVectorImpl &);
195 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
193 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
196194 const SmallVectorImpl &);
197 void cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
195 void cvtStWriteBackRegAddrMode2(MCInst &Inst,
198196 const SmallVectorImpl &);
199 void cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
197 void cvtStWriteBackRegAddrMode3(MCInst &Inst,
200198 const SmallVectorImpl &);
201 void cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
199 void cvtLdExtTWriteBackImm(MCInst &Inst,
202200 const SmallVectorImpl &);
203 void cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
201 void cvtLdExtTWriteBackReg(MCInst &Inst,
204202 const SmallVectorImpl &);
205 void cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
203 void cvtStExtTWriteBackImm(MCInst &Inst,
206204 const SmallVectorImpl &);
207 void cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
205 void cvtStExtTWriteBackReg(MCInst &Inst,
208206 const SmallVectorImpl &);
209 void cvtLdrdPre(MCInst &Inst, unsigned Opcode,
210 const SmallVectorImpl &);
211 void cvtStrdPre(MCInst &Inst, unsigned Opcode,
212 const SmallVectorImpl &);
213 void cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
207 void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl &);
208 void cvtStrdPre(MCInst &Inst, const SmallVectorImpl &);
209 void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
214210 const SmallVectorImpl &);
215 void cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
211 void cvtThumbMultiply(MCInst &Inst,
216212 const SmallVectorImpl &);
217 void cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
213 void cvtVLDwbFixed(MCInst &Inst,
218214 const SmallVectorImpl &);
219 void cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
215 void cvtVLDwbRegister(MCInst &Inst,
220216 const SmallVectorImpl &);
221 void cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
217 void cvtVSTwbFixed(MCInst &Inst,
222218 const SmallVectorImpl &);
223 void cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
219 void cvtVSTwbRegister(MCInst &Inst,
224220 const SmallVectorImpl &);
225
226221 bool validateInstruction(MCInst &Inst,
227222 const SmallVectorImpl &Ops);
228223 bool processInstruction(MCInst &Inst,
38803875 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
38813876 /// when they refer multiple MIOperands inside a single one.
38823877 void ARMAsmParser::
3883 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3878 cvtT2LdrdPre(MCInst &Inst,
38843879 const SmallVectorImpl &Operands) {
38853880 // Rt, Rt2
38863881 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
38973892 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
38983893 /// when they refer multiple MIOperands inside a single one.
38993894 void ARMAsmParser::
3900 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3895 cvtT2StrdPre(MCInst &Inst,
39013896 const SmallVectorImpl &Operands) {
39023897 // Create a writeback register dummy placeholder.
39033898 Inst.addOperand(MCOperand::CreateReg(0));
39143909 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
39153910 /// when they refer multiple MIOperands inside a single one.
39163911 void ARMAsmParser::
3917 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3912 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
39183913 const SmallVectorImpl &Operands) {
39193914 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
39203915
39293924 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
39303925 /// when they refer multiple MIOperands inside a single one.
39313926 void ARMAsmParser::
3932 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3927 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
39333928 const SmallVectorImpl &Operands) {
39343929 // Create a writeback register dummy placeholder.
39353930 Inst.addOperand(MCOperand::CreateImm(0));
39423937 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
39433938 /// when they refer multiple MIOperands inside a single one.
39443939 void ARMAsmParser::
3945 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3940 cvtLdWriteBackRegAddrMode2(MCInst &Inst,
39463941 const SmallVectorImpl &Operands) {
39473942 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
39483943
39573952 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
39583953 /// when they refer multiple MIOperands inside a single one.
39593954 void ARMAsmParser::
3960 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3955 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
39613956 const SmallVectorImpl &Operands) {
39623957 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
39633958
39733968 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
39743969 /// when they refer multiple MIOperands inside a single one.
39753970 void ARMAsmParser::
3976 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3971 cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
39773972 const SmallVectorImpl &Operands) {
39783973 // Create a writeback register dummy placeholder.
39793974 Inst.addOperand(MCOperand::CreateImm(0));
39863981 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
39873982 /// when they refer multiple MIOperands inside a single one.
39883983 void ARMAsmParser::
3989 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3984 cvtStWriteBackRegAddrMode2(MCInst &Inst,
39903985 const SmallVectorImpl &Operands) {
39913986 // Create a writeback register dummy placeholder.
39923987 Inst.addOperand(MCOperand::CreateImm(0));
39993994 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
40003995 /// when they refer multiple MIOperands inside a single one.
40013996 void ARMAsmParser::
4002 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3997 cvtStWriteBackRegAddrMode3(MCInst &Inst,
40033998 const SmallVectorImpl &Operands) {
40043999 // Create a writeback register dummy placeholder.
40054000 Inst.addOperand(MCOperand::CreateImm(0));
40124007 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
40134008 /// when they refer multiple MIOperands inside a single one.
40144009 void ARMAsmParser::
4015 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
4010 cvtLdExtTWriteBackImm(MCInst &Inst,
40164011 const SmallVectorImpl &Operands) {
40174012 // Rt
40184013 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
40304025 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
40314026 /// when they refer multiple MIOperands inside a single one.
40324027 void ARMAsmParser::
4033 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
4028 cvtLdExtTWriteBackReg(MCInst &Inst,
40344029 const SmallVectorImpl &Operands) {
40354030 // Rt
40364031 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
40484043 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
40494044 /// when they refer multiple MIOperands inside a single one.
40504045 void ARMAsmParser::
4051 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
4046 cvtStExtTWriteBackImm(MCInst &Inst,
40524047 const SmallVectorImpl &Operands) {
40534048 // Create a writeback register dummy placeholder.
40544049 Inst.addOperand(MCOperand::CreateImm(0));
40664061 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
40674062 /// when they refer multiple MIOperands inside a single one.
40684063 void ARMAsmParser::
4069 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
4064 cvtStExtTWriteBackReg(MCInst &Inst,
40704065 const SmallVectorImpl &Operands) {
40714066 // Create a writeback register dummy placeholder.
40724067 Inst.addOperand(MCOperand::CreateImm(0));
40844079 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
40854080 /// when they refer multiple MIOperands inside a single one.
40864081 void ARMAsmParser::
4087 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
4082 cvtLdrdPre(MCInst &Inst,
40884083 const SmallVectorImpl &Operands) {
40894084 // Rt, Rt2
40904085 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
41014096 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
41024097 /// when they refer multiple MIOperands inside a single one.
41034098 void ARMAsmParser::
4104 cvtStrdPre(MCInst &Inst, unsigned Opcode,
4099 cvtStrdPre(MCInst &Inst,
41054100 const SmallVectorImpl &Operands) {
41064101 // Create a writeback register dummy placeholder.
41074102 Inst.addOperand(MCOperand::CreateImm(0));
41184113 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
41194114 /// when they refer multiple MIOperands inside a single one.
41204115 void ARMAsmParser::
4121 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
4116 cvtLdWriteBackRegAddrMode3(MCInst &Inst,
41224117 const SmallVectorImpl &Operands) {
41234118 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
41244119 // Create a writeback register dummy placeholder.
41314126 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
41324127 /// when they refer multiple MIOperands inside a single one.
41334128 void ARMAsmParser::
4134 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
4129 cvtThumbMultiply(MCInst &Inst,
41354130 const SmallVectorImpl &Operands) {
41364131 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
41374132 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
41484143 }
41494144
41504145 void ARMAsmParser::
4151 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
4146 cvtVLDwbFixed(MCInst &Inst,
41524147 const SmallVectorImpl &Operands) {
41534148 // Vd
41544149 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
41614156 }
41624157
41634158 void ARMAsmParser::
4164 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
4159 cvtVLDwbRegister(MCInst &Inst,
41654160 const SmallVectorImpl &Operands) {
41664161 // Vd
41674162 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
41764171 }
41774172
41784173 void ARMAsmParser::
4179 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
4174 cvtVSTwbFixed(MCInst &Inst,
41804175 const SmallVectorImpl &Operands) {
41814176 // Create a writeback register dummy placeholder.
41824177 Inst.addOperand(MCOperand::CreateImm(0));
41894184 }
41904185
41914186 void ARMAsmParser::
4192 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
4187 cvtVSTwbRegister(MCInst &Inst,
41934188 const SmallVectorImpl &Operands) {
41944189 // Create a writeback register dummy placeholder.
41954190 Inst.addOperand(MCOperand::CreateImm(0));
17501750
17511751 // Add the handler to the conversion driver function.
17521752 CvtOS << " case CVT_" << AsmMatchConverter << ":\n"
1753 << " " << AsmMatchConverter << "(Inst, Opcode, Operands);\n"
1753 << " " << AsmMatchConverter << "(Inst, Operands);\n"
17541754 << " break;\n";
17551755
17561756 // FIXME: Handle the operand number lookup for custom match functions.