llvm.org GIT mirror llvm / 74e2d6e
Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140470 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
4 changed file(s) with 56 addition(s) and 60 deletion(s). Raw diff Collapse all Expand all
131131 ///
132132 FunctionPass *createPrologEpilogCodeInserter();
133133
134 /// LowerSubregs Pass - This pass lowers subregs to register-register copies
135 /// which yields suboptimal, but correct code if the register allocator
136 /// cannot coalesce all subreg operations during allocation.
137 ///
138 FunctionPass *createLowerSubregsPass();
134 /// ExpandPostRAPseudos Pass - This pass expands pseudo instructions after
135 /// register allocation.
136 ///
137 FunctionPass *createExpandPostRAPseudosPass();
139138
140139 /// createPostRAScheduler - This pass performs post register allocation
141140 /// scheduling.
None //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
0 //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file defines a MachineFunction pass which runs after register
10 // allocation that turns subreg insert/extract instructions into register
11 // copies, as needed. This ensures correct codegen even if the coalescer
12 // isn't able to remove all subreg instructions.
9 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
10 // instructions after register allocation.
1311 //
1412 //===----------------------------------------------------------------------===//
1513
16 #define DEBUG_TYPE "lowersubregs"
14 #define DEBUG_TYPE "postrapseudos"
1715 #include "llvm/CodeGen/Passes.h"
1816 #include "llvm/Function.h"
1917 #include "llvm/CodeGen/MachineFunctionPass.h"
2826 using namespace llvm;
2927
3028 namespace {
31 struct LowerSubregsInstructionPass : public MachineFunctionPass {
32 private:
33 const TargetRegisterInfo *TRI;
34 const TargetInstrInfo *TII;
35
36 public:
37 static char ID; // Pass identification, replacement for typeid
38 LowerSubregsInstructionPass() : MachineFunctionPass(ID) {}
39
40 const char *getPassName() const {
41 return "Subregister lowering instruction pass";
42 }
43
44 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
45 AU.setPreservesCFG();
46 AU.addPreservedID(MachineLoopInfoID);
47 AU.addPreservedID(MachineDominatorsID);
48 MachineFunctionPass::getAnalysisUsage(AU);
49 }
50
51 /// runOnMachineFunction - pass entry point
52 bool runOnMachineFunction(MachineFunction&);
53
54 private:
55 bool LowerSubregToReg(MachineInstr *MI);
56 bool LowerCopy(MachineInstr *MI);
57
58 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
59 const TargetRegisterInfo *TRI);
60 void TransferImplicitDefs(MachineInstr *MI);
61 };
62
63 char LowerSubregsInstructionPass::ID = 0;
64 }
65
66 FunctionPass *llvm::createLowerSubregsPass() {
67 return new LowerSubregsInstructionPass();
29 struct ExpandPostRA : public MachineFunctionPass {
30 private:
31 const TargetRegisterInfo *TRI;
32 const TargetInstrInfo *TII;
33
34 public:
35 static char ID; // Pass identification, replacement for typeid
36 ExpandPostRA() : MachineFunctionPass(ID) {}
37
38 const char *getPassName() const {
39 return "Post-RA pseudo instruction expansion pass";
40 }
41
42 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
43 AU.setPreservesCFG();
44 AU.addPreservedID(MachineLoopInfoID);
45 AU.addPreservedID(MachineDominatorsID);
46 MachineFunctionPass::getAnalysisUsage(AU);
47 }
48
49 /// runOnMachineFunction - pass entry point
50 bool runOnMachineFunction(MachineFunction&);
51
52 private:
53 bool LowerSubregToReg(MachineInstr *MI);
54 bool LowerCopy(MachineInstr *MI);
55
56 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
57 const TargetRegisterInfo *TRI);
58 void TransferImplicitDefs(MachineInstr *MI);
59 };
60 } // end anonymous namespace
61
62 char ExpandPostRA::ID = 0;
63
64 FunctionPass *llvm::createExpandPostRAPseudosPass() {
65 return new ExpandPostRA();
6866 }
6967
7068 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
7169 /// and the lowered replacement instructions immediately precede it.
7270 /// Mark the replacement instructions with the dead flag.
7371 void
74 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
75 unsigned DstReg,
76 const TargetRegisterInfo *TRI) {
72 ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
73 const TargetRegisterInfo *TRI) {
7774 for (MachineBasicBlock::iterator MII =
7875 prior(MachineBasicBlock::iterator(MI)); ; --MII) {
7976 if (MII->addRegisterDead(DstReg, TRI))
8784 /// replacement instructions immediately precede it. Copy any implicit-def
8885 /// operands from MI to the replacement instruction.
8986 void
90 LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
87 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) {
9188 MachineBasicBlock::iterator CopyMI = MI;
9289 --CopyMI;
9390
9996 }
10097 }
10198
102 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
99 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
103100 MachineBasicBlock *MBB = MI->getParent();
104101 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
105102 MI->getOperand(1).isImm() &&
151148 return true;
152149 }
153150
154 bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
151 bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
155152 MachineOperand &DstMO = MI->getOperand(0);
156153 MachineOperand &SrcMO = MI->getOperand(1);
157154
190187 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
191188 /// copies.
192189 ///
193 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
190 bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
194191 DEBUG(dbgs() << "Machine Function\n"
195 << "********** LOWERING SUBREG INSTRS **********\n"
192 << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
196193 << "********** Function: "
197194 << MF.getFunction()->getName() << '\n');
198195 TRI = MF.getTarget().getRegisterInfo();
443443 if (addPostRegAlloc(PM, OptLevel))
444444 printAndVerify(PM, "After PostRegAlloc passes");
445445
446 PM.add(createLowerSubregsPass());
447 printAndVerify(PM, "After LowerSubregs");
446 PM.add(createExpandPostRAPseudosPass());
447 printAndVerify(PM, "After ExpandPostRAPseudos");
448448
449449 // Insert prolog/epilog code. Eliminate abstract frame index references...
450450 PM.add(createPrologEpilogCodeInserter());
322322 if (addPostRegAlloc(PM, OptLevel))
323323 printAndVerify(PM, "After PostRegAlloc passes");
324324
325 PM.add(createLowerSubregsPass());
326 printAndVerify(PM, "After LowerSubregs");
325 PM.add(createExpandPostRAPseudosPass());
326 printAndVerify(PM, "After ExpandPostRAPseudos");
327327
328328 // Insert prolog/epilog code. Eliminate abstract frame index references...
329329 PM.add(createPrologEpilogCodeInserter());