llvm.org GIT mirror llvm / 749c6f6
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 11 years ago
42 changed file(s) with 234 addition(s) and 233 deletion(s). Raw diff Collapse all Expand all
1919
2020 namespace llvm {
2121
22 class TargetInstrDescriptor;
22 class TargetInstrDesc;
2323
2424 template struct ilist_traits;
2525 template struct ilist;
2828 /// MachineInstr - Representation of each machine instruction.
2929 ///
3030 class MachineInstr {
31 const TargetInstrDescriptor *TID; // Instruction descriptor.
31 const TargetInstrDesc *TID; // Instruction descriptor.
3232 unsigned short NumImplicitOps; // Number of implicit operands (which
3333 // are determined at construction time).
3434
5353
5454 /// MachineInstr ctor - This constructor create a MachineInstr and add the
5555 /// implicit operands. It reserves space for number of operands specified by
56 /// TargetInstrDescriptor.
57 explicit MachineInstr(const TargetInstrDescriptor &TID, bool NoImp = false);
56 /// TargetInstrDesc.
57 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
5858
5959 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
6060 /// the MachineInstr is created and added to the end of the specified basic
6161 /// block.
6262 ///
63 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
63 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
6464
6565 ~MachineInstr();
6666
6969
7070 /// getDesc - Returns the target instruction descriptor of this
7171 /// MachineInstr.
72 const TargetInstrDescriptor *getDesc() const { return TID; }
72 const TargetInstrDesc &getDesc() const { return *TID; }
7373
7474 /// getOpcode - Returns the opcode of this MachineInstr.
7575 ///
165165 /// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
166166 /// the current instruction with a new one.
167167 ///
168 void setInstrDescriptor(const TargetInstrDescriptor &tid) { TID = &tid; }
168 void setInstrDescriptor(const TargetInstrDesc &tid) { TID = &tid; }
169169
170170 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
171171 /// fewer operand than it started with.
2121
2222 namespace llvm {
2323
24 class TargetInstrDescriptor;
24 class TargetInstrDesc;
2525
2626 class MachineInstrBuilder {
2727 MachineInstr *MI;
8787 /// BuildMI - Builder interface. Specify how to create the initial instruction
8888 /// itself.
8989 ///
90 inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID) {
90 inline MachineInstrBuilder BuildMI(const TargetInstrDesc &TID) {
9191 return MachineInstrBuilder(new MachineInstr(TID));
9292 }
9393
9494 /// BuildMI - This version of the builder sets up the first operand as a
9595 /// destination virtual register.
9696 ///
97 inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID,
97 inline MachineInstrBuilder BuildMI(const TargetInstrDesc &TID,
9898 unsigned DestReg) {
9999 return MachineInstrBuilder(new MachineInstr(TID)).addReg(DestReg, true);
100100 }
105105 ///
106106 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
107107 MachineBasicBlock::iterator I,
108 const TargetInstrDescriptor &TID,
108 const TargetInstrDesc &TID,
109109 unsigned DestReg) {
110110 MachineInstr *MI = new MachineInstr(TID);
111111 BB.insert(I, MI);
118118 ///
119119 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
120120 MachineBasicBlock::iterator I,
121 const TargetInstrDescriptor &TID) {
121 const TargetInstrDesc &TID) {
122122 MachineInstr *MI = new MachineInstr(TID);
123123 BB.insert(I, MI);
124124 return MachineInstrBuilder(MI);
129129 /// destination register.
130130 ///
131131 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
132 const TargetInstrDescriptor &TID) {
132 const TargetInstrDesc &TID) {
133133 return BuildMI(*BB, BB->end(), TID);
134134 }
135135
138138 /// operand as a destination virtual register.
139139 ///
140140 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
141 const TargetInstrDescriptor &TID,
141 const TargetInstrDesc &TID,
142142 unsigned DestReg) {
143143 return BuildMI(*BB, BB->end(), TID, DestReg);
144144 }
3030 class SelectionDAG;
3131 class SelectionDAGISel;
3232 class TargetInstrInfo;
33 class TargetInstrDescriptor;
33 class TargetInstrDesc;
3434 class TargetMachine;
3535 class TargetRegisterClass;
3636
334334 DenseMap &VRBaseMap);
335335
336336 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
337 const TargetInstrDescriptor &II,
337 const TargetInstrDesc &II,
338338 DenseMap &VRBaseMap);
339339
340340 void EmitSchedule();
352352 DenseMap &VRBaseMap);
353353
354354 void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
355 const TargetInstrDescriptor *II,
355 const TargetInstrDesc *II,
356356 DenseMap &VRBaseMap);
357357 };
358358
8181 // Machine Instruction Flags and Description
8282 //===----------------------------------------------------------------------===//
8383
84 /// TargetInstrDescriptor flags - These should be considered private to the
85 /// implementation of the TargetInstrDescriptor class. Clients should use the
86 /// predicate methods on TargetInstrDescriptor, not use these directly. These
87 /// all correspond to bitfields in the TargetInstrDescriptor::Flags field.
84 /// TargetInstrDesc flags - These should be considered private to the
85 /// implementation of the TargetInstrDesc class. Clients should use the
86 /// predicate methods on TargetInstrDesc, not use these directly. These
87 /// all correspond to bitfields in the TargetInstrDesc::Flags field.
8888 namespace TID {
8989 enum {
9090 Variadic = 0,
110110 };
111111 }
112112
113 /// TargetInstrDescriptor - Describe properties that are true of each
113 /// TargetInstrDesc - Describe properties that are true of each
114114 /// instruction in the target description file. This captures information about
115115 /// side effects, register use and many other things. There is one instance of
116116 /// this struct for each target instruction class, and the MachineInstr class
117117 /// points to this struct directly to describe itself.
118 class TargetInstrDescriptor {
118 class TargetInstrDesc {
119119 public:
120120 unsigned short Opcode; // The opcode number.
121121 unsigned short NumOperands; // Num of args (may be more if variable_ops)
146146 /// dest operand. Returns -1 if there isn't one.
147147 int findTiedToSrcOperand(unsigned OpNum) const;
148148
149 /// getOpcode - Return the opcode number for this descriptor.
150 unsigned getOpcode() const {
151 return Opcode;
152 }
153
149154 /// getName - Return the name of the record in the .td file for this
150155 /// instruction, for example "ADD8ri".
151156 const char *getName() const {
420425 /// TargetInstrInfo - Interface to description of machine instructions
421426 ///
422427 class TargetInstrInfo {
423 const TargetInstrDescriptor* desc; // raw array to allow static init'n
424 unsigned NumOpcodes; // number of entries in the desc array
425 unsigned numRealOpCodes; // number of non-dummy op codes
428 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
429 unsigned NumOpcodes; // Number of entries in the desc array
426430
427431 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
428432 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
429433 public:
430 TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
434 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
431435 virtual ~TargetInstrInfo();
432436
433437 // Invariant opcodes: All instruction sets have these as their low opcodes.
444448 /// get - Return the machine instruction descriptor that corresponds to the
445449 /// specified instruction opcode.
446450 ///
447 const TargetInstrDescriptor& get(unsigned Opcode) const {
448 assert(Opcode < NumOpcodes);
449 return desc[Opcode];
451 const TargetInstrDesc &get(unsigned Opcode) const {
452 assert(Opcode < NumOpcodes && "Invalid opcode!");
453 return Descriptors[Opcode];
450454 }
451455
452456 /// isTriviallyReMaterializable - Return true if the instruction is trivially
453457 /// rematerializable, meaning it has no side effects and requires no operands
454458 /// that aren't always available.
455459 bool isTriviallyReMaterializable(MachineInstr *MI) const {
456 return MI->getDesc()->isRematerializable() &&
460 return MI->getDesc().isRematerializable() &&
457461 isReallyTriviallyReMaterializable(MI);
458462 }
459463
461465 /// effects that are not captured by any operands of the instruction or other
462466 /// flags.
463467 bool hasUnmodelledSideEffects(MachineInstr *MI) const {
464 const TargetInstrDescriptor *TID = MI->getDesc();
465 if (TID->hasNoSideEffects()) return false;
466 if (!TID->hasConditionalSideEffects()) return true;
468 const TargetInstrDesc &TID = MI->getDesc();
469 if (TID.hasNoSideEffects()) return false;
470 if (!TID.hasConditionalSideEffects()) return true;
467471 return !isReallySideEffectFree(MI); // May have side effects
468472 }
469473 protected:
772776 /// libcodegen, not in libtarget.
773777 class TargetInstrInfoImpl : public TargetInstrInfo {
774778 protected:
775 TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
779 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
776780 : TargetInstrInfo(desc, NumOpcodes) {}
777781 public:
778782 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
2323 class TargetData;
2424 class TargetSubtarget;
2525 class TargetInstrInfo;
26 class TargetInstrDescriptor;
2726 class TargetJITInfo;
2827 class TargetLowering;
2928 class TargetFrameInfo;
348348 MachineBasicBlock::iterator E) {
349349 unsigned Time = 0;
350350 for (; I != E; ++I) {
351 const TargetInstrDescriptor *TID = I->getDesc();
352 if (TID->isCall())
351 const TargetInstrDesc &TID = I->getDesc();
352 if (TID.isCall())
353353 Time += 10;
354 else if (TID->isSimpleLoad() || TID->mayStore())
354 else if (TID.isSimpleLoad() || TID.mayStore())
355355 Time += 2;
356356 else
357357 ++Time;
777777
778778 MachineInstr *MBB1I = --MBB1->end();
779779 MachineInstr *MBB2I = --MBB2->end();
780 return MBB2I->getDesc()->isCall() && !MBB1I->getDesc()->isCall();
780 return MBB2I->getDesc().isCall() && !MBB1I->getDesc().isCall();
781781 }
782782
783783 /// OptimizeBlock - Analyze and optimize control flow related to the specified
957957 // If this branch is the only thing in its block, see if we can forward
958958 // other blocks across it.
959959 if (CurTBB && CurCond.empty() && CurFBB == 0 &&
960 MBB->begin()->getDesc()->isBranch() && CurTBB != MBB) {
960 MBB->begin()->getDesc().isBranch() && CurTBB != MBB) {
961961 // This block may contain just an unconditional branch. Because there can
962962 // be 'non-branch terminators' in the block, try removing the branch and
963963 // then seeing if the block is empty.
358358 BBE = MF.end(); BBI != BBE; ++BBI)
359359 for (MachineBasicBlock::iterator MI = BBI->begin(),
360360 ME = BBI->end(); MI != ME; ++MI)
361 if (MI->getDesc()->isCall())
361 if (MI->getDesc().isCall())
362362 VisitCallPoint(*MI);
363363 }
364364
31523152 for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
31533153 MI != E; ++MI) {
31543154 if (MI->getOpcode() != TargetInstrInfo::LABEL) {
3155 SawPotentiallyThrowing |= MI->getDesc()->isCall();
3155 SawPotentiallyThrowing |= MI->getDesc().isCall();
31563156 continue;
31573157 }
31583158
459459 MachineBasicBlock::iterator I = BB->end();
460460 while (I != BB->begin()) {
461461 --I;
462 if (!I->getDesc()->isBranch())
462 if (!I->getDesc().isBranch())
463463 break;
464464 }
465465 return I;
547547 bool SeenCondBr = false;
548548 for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end();
549549 I != E; ++I) {
550 const TargetInstrDescriptor *TID = I->getDesc();
551 if (TID->isNotDuplicable())
550 const TargetInstrDesc &TID = I->getDesc();
551 if (TID.isNotDuplicable())
552552 BBI.CannotBeCopied = true;
553553
554554 bool isPredicated = TII->isPredicated(I);
555 bool isCondBr = BBI.IsBrAnalyzable && TID->isConditionalBranch();
555 bool isCondBr = BBI.IsBrAnalyzable && TID.isConditionalBranch();
556556
557557 if (!isCondBr) {
558558 if (!isPredicated)
589589 if (TII->DefinesPredicate(I, PredDefs))
590590 BBI.ClobbersPred = true;
591591
592 if (!TID->isPredicable()) {
592 if (!TID.isPredicable()) {
593593 BBI.IsUnpredicable = true;
594594 return;
595595 }
11311131 bool IgnoreBr) {
11321132 for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
11331133 E = FromBBI.BB->end(); I != E; ++I) {
1134 const TargetInstrDescriptor *TID = I->getDesc();
1134 const TargetInstrDesc &TID = I->getDesc();
11351135 bool isPredicated = TII->isPredicated(I);
11361136 // Do not copy the end of the block branches.
1137 if (IgnoreBr && !isPredicated && TID->isBranch())
1137 if (IgnoreBr && !isPredicated && TID.isBranch())
11381138 break;
11391139
11401140 MachineInstr *MI = I->clone();
614614 return false;
615615
616616 isLoad = false;
617 const TargetInstrDescriptor *TID = MI->getDesc();
618 if (TID->isImplicitDef() || tii_->isTriviallyReMaterializable(MI)) {
619 isLoad = TID->isSimpleLoad();
617 const TargetInstrDesc &TID = MI->getDesc();
618 if (TID.isImplicitDef() || tii_->isTriviallyReMaterializable(MI)) {
619 isLoad = TID.isSimpleLoad();
620620 return true;
621621 }
622622
678678 SmallVector &Ops,
679679 bool isSS, int Slot, unsigned Reg) {
680680 unsigned MRInfo = 0;
681 const TargetInstrDescriptor *TID = MI->getDesc();
681 const TargetInstrDesc &TID = MI->getDesc();
682682 // If it is an implicit def instruction, just delete it.
683 if (TID->isImplicitDef()) {
683 if (TID.isImplicitDef()) {
684684 RemoveMachineInstrFromMaps(MI);
685685 vrm.RemoveMachineInstrFromMaps(MI);
686686 MI->eraseFromParent();
698698 MRInfo |= (unsigned)VirtRegMap::isMod;
699699 else {
700700 // Filter out two-address use operand(s).
701 if (TID->getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
701 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
702702 MRInfo = VirtRegMap::isModRef;
703703 continue;
704704 }
12241224 int LdSlot = 0;
12251225 bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
12261226 bool isLoad = isLoadSS ||
1227 (DefIsReMat && (ReMatDefMI->getDesc()->isSimpleLoad()));
1227 (DefIsReMat && (ReMatDefMI->getDesc().isSimpleLoad()));
12281228 bool IsFirstRange = true;
12291229 for (LiveInterval::Ranges::const_iterator
12301230 I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
13061306 int LdSlot = 0;
13071307 bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
13081308 bool isLoad = isLoadSS ||
1309 (DefIsReMat && ReMatDefMI->getDesc()->isSimpleLoad());
1309 (DefIsReMat && ReMatDefMI->getDesc().isSimpleLoad());
13101310 rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
13111311 Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
13121312 CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo,
14211421 int LdSlot = 0;
14221422 bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
14231423 // If the rematerializable def is a load, also try to fold it.
1424 if (isLoadSS || ReMatDefMI->getDesc()->isSimpleLoad())
1424 if (isLoadSS || ReMatDefMI->getDesc().isSimpleLoad())
14251425 Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
14261426 Ops, isLoadSS, LdSlot, VReg);
14271427 }
14491449 MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
14501450 int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg);
14511451 assert(UseIdx != -1);
1452 if (LastUse->getDesc()->getOperandConstraint(UseIdx, TOI::TIED_TO) ==
1452 if (LastUse->getDesc().getOperandConstraint(UseIdx, TOI::TIED_TO) ==
14531453 -1) {
14541454 LastUse->getOperand(UseIdx).setIsKill();
14551455 vrm.addKillPoint(LI->reg, LastUseIdx);
534534
535535 // Finally, if the last instruction in the block is a return, make sure to mark
536536 // it as using all of the live-out values in the function.
537 if (!MBB->empty() && MBB->back().getDesc()->isReturn()) {
537 if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
538538 MachineInstr *Ret = &MBB->back();
539539 for (MachineRegisterInfo::liveout_iterator
540540 I = MF->getRegInfo().liveout_begin(),
131131
132132 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
133133 iterator I = end();
134 while (I != begin() && (--I)->getDesc()->isTerminator())
134 while (I != begin() && (--I)->getDesc().isTerminator())
135135 ; /*noop */
136 if (I != end() && !I->getDesc()->isTerminator()) ++I;
136 if (I != end() && !I->getDesc().isTerminator()) ++I;
137137 return I;
138138 }
139139
260260 MachineBasicBlock::iterator I = end();
261261 while (I != begin()) {
262262 --I;
263 if (!I->getDesc()->isTerminator()) break;
263 if (!I->getDesc().isTerminator()) break;
264264
265265 // Scan the operands of this machine instruction, replacing any uses of Old
266266 // with New.
247247
248248 /// MachineInstr ctor - This constructor create a MachineInstr and add the
249249 /// implicit operands. It reserves space for number of operands specified by
250 /// TargetInstrDescriptor or the numOperands if it is not zero. (for
250 /// TargetInstrDesc or the numOperands if it is not zero. (for
251251 /// instructions with variable number of operands).
252 MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
252 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
253253 : TID(&tid), NumImplicitOps(0), Parent(0) {
254254 if (!NoImp && TID->getImplicitDefs())
255255 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
268268 /// MachineInstr is created and added to the end of the specified basic block.
269269 ///
270270 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
271 const TargetInstrDescriptor &tid)
271 const TargetInstrDesc &tid)
272272 : TID(&tid), NumImplicitOps(0), Parent(0) {
273273 assert(MBB && "Cannot use inserting ctor with null basic block!");
274274 if (TID->ImplicitDefs)
287287 /// MachineInstr ctor - Copies MachineInstr arg exactly
288288 ///
289289 MachineInstr::MachineInstr(const MachineInstr &MI) {
290 TID = MI.getDesc();
290 TID = &MI.getDesc();
291291 NumImplicitOps = MI.NumImplicitOps;
292292 Operands.reserve(MI.getNumOperands());
293293
536536 /// operand list that is used to represent the predicate. It returns -1 if
537537 /// none is found.
538538 int MachineInstr::findFirstPredOperandIdx() const {
539 const TargetInstrDescriptor *TID = getDesc();
540 if (TID->isPredicable()) {
539 const TargetInstrDesc &TID = getDesc();
540 if (TID.isPredicable()) {
541541 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
542 if (TID->OpInfo[i].isPredicate())
542 if (TID.OpInfo[i].isPredicate())
543543 return i;
544544 }
545545
549549 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
550550 /// to two addr elimination.
551551 bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
552 const TargetInstrDescriptor *TID = getDesc();
552 const TargetInstrDesc &TID = getDesc();
553553 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
554554 const MachineOperand &MO1 = getOperand(i);
555555 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
556556 for (unsigned j = i+1; j < e; ++j) {
557557 const MachineOperand &MO2 = getOperand(j);
558558 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
559 TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
559 TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
560560 return true;
561561 }
562562 }
586586
587587 /// copyPredicates - Copies predicate operand(s) from MI.
588588 void MachineInstr::copyPredicates(const MachineInstr *MI) {
589 const TargetInstrDescriptor *TID = MI->getDesc();
590 if (TID->isPredicable()) {
589 const TargetInstrDesc &TID = MI->getDesc();
590 if (TID.isPredicable()) {
591591 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
592 if (TID->OpInfo[i].isPredicate()) {
592 if (TID.OpInfo[i].isPredicate()) {
593593 // Predicated operands must be last operands.
594594 addOperand(MI->getOperand(i));
595595 }
610610 ++StartOp; // Don't print this operand again!
611611 }
612612
613 OS << getDesc()->Name;
613 OS << getDesc().getName();
614614
615615 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
616616 if (i != StartOp)
224224 bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
225225 DEBUG({
226226 DOUT << "--- Checking if we can hoist " << I;
227 if (I.getDesc()->ImplicitUses) {
227 if (I.getDesc().getImplicitUses()) {
228228 DOUT << " * Instruction has implicit uses:\n";
229229
230230 const MRegisterInfo *MRI = TM->getRegisterInfo();
231 for (const unsigned *ImpUses = I.getDesc()->ImplicitUses;
231 for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
232232 *ImpUses; ++ImpUses)
233233 DOUT << " -> " << MRI->getName(*ImpUses) << "\n";
234234 }
235235
236 if (I.getDesc()->ImplicitDefs) {
236 if (I.getDesc().getImplicitDefs()) {
237237 DOUT << " * Instruction has implicit defines:\n";
238238
239239 const MRegisterInfo *MRI = TM->getRegisterInfo();
240 for (const unsigned *ImpDefs = I.getDesc()->ImplicitDefs;
240 for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
241241 *ImpDefs; ++ImpDefs)
242242 DOUT << " -> " << MRI->getName(*ImpDefs) << "\n";
243243 }
261261 // Add code to restore the callee-save registers in each exiting block.
262262 for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI)
263263 // If last instruction is a return instruction, add an epilogue.
264 if (!FI->empty() && FI->back().getDesc()->isReturn()) {
264 if (!FI->empty() && FI->back().getDesc().isReturn()) {
265265 MBB = FI;
266266 I = MBB->end(); --I;
267267
268268 // Skip over all terminator instructions, which are part of the return
269269 // sequence.
270270 MachineBasicBlock::iterator I2 = I;
271 while (I2 != MBB->begin() && (--I2)->getDesc()->isTerminator())
271 while (I2 != MBB->begin() && (--I2)->getDesc().isTerminator())
272272 I = I2;
273273
274274 bool AtStart = I == MBB->begin();
484484 // Add epilogue to restore the callee-save registers in each exiting block
485485 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
486486 // If last instruction is a return instruction, add an epilogue
487 if (!I->empty() && I->back().getDesc()->isReturn())
487 if (!I->empty() && I->back().getDesc().isReturn())
488488 Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I);
489489 }
490490 }
648648 while (MII != MBB.end()) {
649649 MachineInstr *MI = MII++;
650650 MBBCurTime++;
651 const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
651 const TargetInstrDesc &TID = MI->getDesc();
652652 DEBUG(DOUT << "\nTime=" << MBBCurTime << " Starting RegAlloc of: " << *MI;
653653 DOUT << " Regs have values: ";
654654 for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
749749 }
750750
751751 // Loop over the implicit defs, spilling them as well.
752 if (TID.ImplicitDefs) {
753 for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
752 if (TID.getImplicitDefs()) {
753 for (const unsigned *ImplicitDefs = TID.getImplicitDefs();
754754 *ImplicitDefs; ++ImplicitDefs) {
755755 unsigned Reg = *ImplicitDefs;
756756 if (PhysRegsUsed[Reg] != -2) {
562562 // Otherwise, sequentially allocate each instruction in the MBB.
563563 while (MII != MBB.end()) {
564564 MachineInstr *MI = MII++;
565 const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
565 const TargetInstrDesc &TID = MI->getDesc();
566566 DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
567567 DOUT << " Regs have values: ";
568568 for (unsigned i = 0; i != MRI->getNumRegs(); ++i)
172172
173173 // This is a preliminary pass that will invalidate any registers that are
174174 // used by the instruction (including implicit uses).
175 const TargetInstrDescriptor &Desc = *MI->getDesc();
175 const TargetInstrDesc &Desc = MI->getDesc();
176176 const unsigned *Regs;
177177 if (Desc.ImplicitUses) {
178178 for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
202202 unsigned physReg = Virt2PhysRegMap[virtualReg];
203203 if (physReg == 0) {
204204 if (op.isDef()) {
205 int TiedOp = MI->getDesc()->findTiedToSrcOperand(i);
205 int TiedOp = Desc.findTiedToSrcOperand(i);
206206 if (TiedOp == -1) {
207207 physReg = getFreeReg(virtualReg);
208208 } else {
9191 }
9292
9393 MachineInstr *MI = MBBI;
94 const TargetInstrDesc &TID = MI->getDesc();
9495
9596 // Reaching a terminator instruction. Restore a scavenged register (which
9697 // must be life out.
97 if (MI->getDesc()->isTerminator())
98 if (TID.isTerminator())
9899 restoreScavengedReg();
99100
100101 // Process uses first.
121122 setUnused(ChangedRegs);
122123
123124 // Process defs.
124 const TargetInstrDescriptor *TID = MI->getDesc();
125125 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
126126 const MachineOperand &MO = MI->getOperand(i);
127127 if (!MO.isRegister() || !MO.isDef())
133133 continue;
134134 }
135135 // Skip two-address destination operand.
136 if (TID->findTiedToSrcOperand(i) != -1) {
136 if (TID.findTiedToSrcOperand(i) != -1) {
137137 assert(isUsed(Reg) && "Using an undefined register!");
138138 continue;
139139 }
151151
152152 MachineInstr *MI = MBBI;
153153 // Process defs first.
154 const TargetInstrDescriptor *TID = MI->getDesc();
154 const TargetInstrDesc &TID = MI->getDesc();
155155 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
156156 const MachineOperand &MO = MI->getOperand(i);
157157 if (!MO.isRegister() || !MO.isDef())
158158 continue;
159159 // Skip two-address destination operand.
160 if (TID->findTiedToSrcOperand(i) != -1)
160 if (TID.findTiedToSrcOperand(i) != -1)
161161 continue;
162162 unsigned Reg = MO.getReg();
163163 assert(isUsed(Reg));
5050
5151 unsigned ResNo = Use->getOperand(2).ResNo;
5252 if (Def->isTargetOpcode()) {
53 const TargetInstrDescriptor &II = TII->get(Def->getTargetOpcode());
53 const TargetInstrDesc &II = TII->get(Def->getTargetOpcode());
5454 if (ResNo >= II.getNumDefs() &&
5555 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
5656 PhysReg = Reg;
147147
148148 if (MainNode->isTargetOpcode()) {
149149 unsigned Opc = MainNode->getTargetOpcode();
150 const TargetInstrDescriptor &TID = TII->get(Opc);
150 const TargetInstrDesc &TID = TII->get(Opc);
151151 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
152152 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
153153 SU->isTwoAddress = true;
290290 static const TargetRegisterClass *getInstrOperandRegClass(
291291 const MRegisterInfo *MRI,
292292 const TargetInstrInfo *TII,
293 const TargetInstrDescriptor *II,
293 const TargetInstrDesc &II,
294294 unsigned Op) {
295 if (Op >= II->getNumOperands()) {
296 assert(II->isVariadic() && "Invalid operand # of instruction");
295 if (Op >= II.getNumOperands()) {
296 assert(II.isVariadic() && "Invalid operand # of instruction");
297297 return NULL;
298298 }
299 if (II->OpInfo[Op].isLookupPtrRegClass())
299 if (II.OpInfo[Op].isLookupPtrRegClass())
300300 return TII->getPointerRegClass();
301 return MRI->getRegClass(II->OpInfo[Op].RegClass);
301 return MRI->getRegClass(II.OpInfo[Op].RegClass);
302302 }
303303
304304 void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
370370
371371 void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
372372 MachineInstr *MI,
373 const TargetInstrDescriptor &II,
373 const TargetInstrDesc &II,
374374 DenseMap &VRBaseMap) {
375375 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
376376 // If the specific node value is only used by a CopyToReg and the dest reg
395395 // Create the result registers for this node and add the result regs to
396396 // the machine instruction.
397397 if (VRBase == 0) {
398 const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
398 const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, i);
399399 assert(RC && "Isn't a register operand!");
400400 VRBase = RegInfo.createVirtualRegister(RC);
401401 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
421421 /// assertions only.
422422 void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
423423 unsigned IIOpNum,
424 const TargetInstrDescriptor *II,
424 const TargetInstrDesc *II,
425425 DenseMap &VRBaseMap) {
426426 if (Op.isTargetOpcode()) {
427427 // Note that this case is redundant with the final else block, but we
433433
434434 // Get/emit the operand.
435435 unsigned VReg = getVR(Op, VRBaseMap);
436 const TargetInstrDescriptor *TID = MI->getDesc();
437 bool isOptDef = (IIOpNum < TID->getNumOperands())
438 ? (TID->OpInfo[IIOpNum].isOptionalDef()) : false;
436 const TargetInstrDesc &TID = MI->getDesc();
437 bool isOptDef = (IIOpNum < TID.getNumOperands())
438 ? (TID.OpInfo[IIOpNum].isOptionalDef()) : false;
439439 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
440440
441441 // Verify that it is right.
442442 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
443443 if (II) {
444444 const TargetRegisterClass *RC =
445 getInstrOperandRegClass(MRI, TII, II, IIOpNum);
445 getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
446446 assert(RC && "Don't have operand info for this instruction!");
447447 const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
448448 if (VRC != RC) {
506506 assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
507507 if (II) {
508508 const TargetRegisterClass *RC =
509 getInstrOperandRegClass(MRI, TII, II, IIOpNum);
509 getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
510510 assert(RC && "Don't have operand info for this instruction!");
511511 assert(RegInfo.getRegClass(VReg) == RC &&
512512 "Register class of operand and regclass of use don't agree!");
668668 return;
669669 }
670670
671 const TargetInstrDescriptor &II = TII->get(Opc);
671 const TargetInstrDesc &II = TII->get(Opc);
672672
673673 unsigned NumResults = CountResults(Node);
674674 unsigned NodeOperands = CountOperands(Node);
147147 if (!SU || !SU->Node) continue;
148148 if (SU->isCommutable) {
149149 unsigned Opc = SU->Node->getTargetOpcode();
150 const TargetInstrDescriptor &TID = TII->get(Opc);
150 const TargetInstrDesc &TID = TII->get(Opc);
151151 unsigned NumRes = TID.getNumDefs();
152152 unsigned NumOps = CountOperands(SU->Node);
153153 for (unsigned j = 0; j != NumOps; ++j) {
430430
431431 SUnit *NewSU = NewSUnit(N);
432432 SUnitMap[N].push_back(NewSU);
433 const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
433 const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
434434 for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
435435 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
436436 NewSU->isTwoAddress = true;
621621 /// FIXME: Move to SelectionDAG?
622622 static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg,
623623 const TargetInstrInfo *TII) {
624 const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
624 const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
625625 assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
626626 unsigned NumRes = TID.getNumDefs();
627627 for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
664664 SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
665665 if (!Node || !Node->isTargetOpcode())
666666 continue;
667 const TargetInstrDescriptor &TID = TII->get(Node->getTargetOpcode());
667 const TargetInstrDesc &TID = TII->get(Node->getTargetOpcode());
668668 if (!TID.ImplicitDefs)
669669 continue;
670670 for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
12871287 bool BURegReductionPriorityQueue::canClobber(SUnit *SU, SUnit *Op) {
12881288 if (SU->isTwoAddress) {
12891289 unsigned Opc = SU->Node->getTargetOpcode();
1290 const TargetInstrDescriptor &TID = TII->get(Opc);
1290 const TargetInstrDesc &TID = TII->get(Opc);
12911291 unsigned NumRes = TID.getNumDefs();
12921292 unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
12931293 for (unsigned i = 0; i != NumOps; ++i) {
13631363 continue;
13641364
13651365 unsigned Opc = Node->getTargetOpcode();
1366 const TargetInstrDescriptor &TID = TII->get(Opc);
1366 const TargetInstrDesc &TID = TII->get(Opc);
13671367 unsigned NumRes = TID.getNumDefs();
13681368 unsigned NumOps = ScheduleDAG::CountOperands(Node);
13691369 for (unsigned j = 0; j != NumOps; ++j) {
3434 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
3535 const std::vector &Pred) const {
3636 bool MadeChange = false;
37 const TargetInstrDescriptor *TID = MI->getDesc();
38 if (TID->isPredicable()) {
39 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
40 if (TID->OpInfo[i].isPredicate()) {
41 MachineOperand &MO = MI->getOperand(i);
42 if (MO.isReg()) {
43 MO.setReg(Pred[j].getReg());
44 MadeChange = true;
45 } else if (MO.isImm()) {
46 MO.setImm(Pred[j].getImm());
47 MadeChange = true;
48 } else if (MO.isMBB()) {
49 MO.setMBB(Pred[j].getMBB());
50 MadeChange = true;
51 }
52 ++j;
37 const TargetInstrDesc &TID = MI->getDesc();
38 if (!TID.isPredicable())
39 return false;
40
41 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
42 if (TID.OpInfo[i].isPredicate()) {
43 MachineOperand &MO = MI->getOperand(i);
44 if (MO.isReg()) {
45 MO.setReg(Pred[j].getReg());
46 MadeChange = true;
47 } else if (MO.isImm()) {
48 MO.setImm(Pred[j].getImm());
49 MadeChange = true;
50 } else if (MO.isMBB()) {
51 MO.setMBB(Pred[j].getMBB());
52 MadeChange = true;
5353 }
54 ++j;
5455 }
5556 }
5657 return MadeChange;
9292 mbbi != mbbe; ++mbbi) {
9393 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
9494 mi != me; ++mi) {
95 const TargetInstrDescriptor *TID = mi->getDesc();
95 const TargetInstrDesc &TID = mi->getDesc();
9696
9797 bool FirstTied = true;
98 for (unsigned si = 1, e = TID->getNumOperands(); si < e; ++si) {
99 int ti = TID->getOperandConstraint(si, TOI::TIED_TO);
98 for (unsigned si = 1, e = TID.getNumOperands(); si < e; ++si) {
99 int ti = TID.getOperandConstraint(si, TOI::TIED_TO);
100100 if (ti == -1)
101101 continue;
102102
143143 // so, swap the B and C operands. This makes the live ranges of A
144144 // and C joinable.
145145 // FIXME: This code also works for A := B op C instructions.
146 if (TID->isCommutable() && mi->getNumOperands() >= 3) {
146 if (TID.isCommutable() && mi->getNumOperands() >= 3) {
147147 assert(mi->getOperand(3-si).isRegister() &&
148148 "Not a proper commutative instruction!");
149149 unsigned regC = mi->getOperand(3-si).getReg();
171171
172172 // If this instruction is potentially convertible to a true
173173 // three-address instruction,
174 if (TID->isConvertibleTo3Addr()) {
174 if (TID.isConvertibleTo3Addr()) {
175175 // FIXME: This assumes there are no more operands which are tied
176176 // to another register.
177177 #ifndef NDEBUG
178 for (unsigned i = si+1, e = TID->getNumOperands(); i < e; ++i)
179 assert(TID->getOperandConstraint(i, TOI::TIED_TO) == -1);
178 for (unsigned i = si+1, e = TID.getNumOperands(); i < e; ++i)
179 assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
180180 #endif
181181
182182 if (MachineInstr *New = TII.convertToThreeAddress(mbbi, mi, LV)) {
536536 /// over.
537537 static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
538538 std::vector &KillOps) {
539 const TargetInstrDescriptor *TID = MI.getDesc();
539 const TargetInstrDesc &TID = MI.getDesc();
540540 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
541541 MachineOperand &MO = MI.getOperand(i);
542542 if (!MO.isRegister() || !MO.isUse())
551551 KillOps[Reg]->setIsKill(false);
552552 KillOps[Reg] = NULL;
553553 RegKills.reset(Reg);
554 if (i < TID->getNumOperands() &&
555 TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
554 if (i < TID.getNumOperands() &&
555 TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
556556 // Unless it's a two-address operand, this is the new kill.
557557 MO.setIsKill();
558558 }
965965 NextMII = next(MII);
966966
967967 MachineInstr &MI = *MII;
968 const TargetInstrDescriptor *TID = MI.getDesc();
968 const TargetInstrDesc &TID = MI.getDesc();
969969
970970 // Insert restores here if asked to.
971971 if (VRM.isRestorePt(&MI)) {
10811081 // aren't allowed to modify the reused register. If none of these cases
10821082 // apply, reuse it.
10831083 bool CanReuse = true;
1084 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
1084 int ti = TID.getOperandConstraint(i, TOI::TIED_TO);
10851085 if (ti != -1 &&
10861086 MI.getOperand(ti).isRegister() &&
10871087 MI.getOperand(ti).getReg() == VirtReg) {
12331233 Spills.addAvailable(SSorRMId, &MI, PhysReg);
12341234 // Assumes this is the last use. IsKill will be unset if reg is reused
12351235 // unless it's a two-address operand.
1236 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
1236 if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
12371237 MI.getOperand(i).setIsKill();
12381238 unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
12391239 MI.getOperand(i).setReg(RReg);
14351435 // If this def is part of a two-address operand, make sure to execute
14361436 // the store from the correct physical register.
14371437 unsigned PhysReg;
1438 int TiedOp = MI.getDesc()->findTiedToSrcOperand(i);
1438 int TiedOp = MI.getDesc().findTiedToSrcOperand(i);
14391439 if (TiedOp != -1) {
14401440 PhysReg = MI.getOperand(TiedOp).getReg();
14411441 if (SubIdx) {
5454
5555 void emitInstruction(const MachineInstr &MI);
5656 int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
57 unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID);
57 unsigned getBaseOpcodeFor(const TargetInstrDesc &TID);
5858 unsigned getBinaryCodeForInstr(const MachineInstr &MI);
5959
6060 void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
102102 }
103103
104104 /// getBaseOpcodeFor - Return the opcode value
105 unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) {
106 return (TID->TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
105 unsigned Emitter::getBaseOpcodeFor(const TargetInstrDesc &TID) {
106 return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
107107 }
108108
109109 /// getShiftOp - Verify which is the shift opcode (bit[6:5]) of the
200200 }
201201
202202 unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
203 const TargetInstrDescriptor *Desc = MI.getDesc();
204 unsigned opcode = Desc->Opcode;
203 const TargetInstrDesc &Desc = MI.getDesc();
204 unsigned opcode = Desc.Opcode;
205205 // initial instruction mask
206206 unsigned Value = 0xE0000000;
207207 unsigned op;
208208
209 switch (Desc->TSFlags & ARMII::AddrModeMask) {
209 switch (Desc.TSFlags & ARMII::AddrModeMask) {
210210 case ARMII::AddrModeNone: {
211 switch(Desc->TSFlags & ARMII::FormMask) {
211 switch(Desc.TSFlags & ARMII::FormMask) {
212212 default: {
213213 assert(0 && "Unknown instruction subtype!");
214214 // treat special instruction CLZ
240240 unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
241241 Value |= BaseOpcode << 4;
242242
243 unsigned Format = (Desc->TSFlags & ARMII::FormMask);
243 unsigned Format = (Desc.TSFlags & ARMII::FormMask);
244244 if (Format == ARMII::MulSMUL)
245245 Value |= 1 << 22;
246246
341341
342342 // treat 3 special instructions: MOVsra_flag, MOVsrl_flag and
343343 // MOVrx.
344 unsigned Format = (Desc->TSFlags & ARMII::FormMask);
344 unsigned Format = Desc.TSFlags & ARMII::FormMask;
345345 if (Format == ARMII::DPRdMisc) {
346346 Value |= getMachineOpValue(MI,0) << ARMII::RegRdShift;
347347 Value |= getMachineOpValue(MI,1);
498498 // bit 26 is always 1
499499 Value |= 1 << 26;
500500
501 unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
501 unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
502502 // if the instruction uses offset addressing or pre-indexed addressing,
503503 // set bit P(24) to 1
504504 if (Index == ARMII::IndexModePre || Index == 0)
507507 if (Index == ARMII::IndexModePre)
508508 Value |= 1 << 21;
509509
510 unsigned Format = (Desc->TSFlags & ARMII::FormMask);
510 unsigned Format = Desc.TSFlags & ARMII::FormMask;
511511 // If it is a load instruction (except LDRD), set bit L(20) to 1
512512 if (Format == ARMII::LdFrm)
513513 Value |= 1 << ARMII::L_BitShift;
554554 break;
555555 }
556556 case ARMII::AddrMode3: {
557
558 unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
557 unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
559558 // if the instruction uses offset addressing or pre-indexed addressing,
560559 // set bit P(24) to 1
561560 if (Index == ARMII::IndexModePre || Index == 0)
562561 Value |= 1 << ARMII::IndexShift;
563562
564 unsigned Format = (Desc->TSFlags & ARMII::FormMask);
563 unsigned Format = Desc.TSFlags & ARMII::FormMask;
565564 // If it is a load instruction (except LDRD), set bit L(20) to 1
566565 if (Format == ARMII::LdFrm && opcode != ARM::LDRD)
567566 Value |= 1 << ARMII::L_BitShift;
606605 // bit 27 is always 1
607606 Value |= 1 << 27;
608607
609 unsigned Format = (Desc->TSFlags & ARMII::FormMask);
608 unsigned Format = Desc.TSFlags & ARMII::FormMask;
610609 // if it is a load instr, set bit L(20) to 1
611610 if (Format == ARMII::LdFrm)
612611 Value |= 1 << ARMII::L_BitShift;
370370 MBBSize += ARM::GetInstSize(I);
371371
372372 int Opc = I->getOpcode();
373 if (I->getDesc()->isBranch()) {
373 if (I->getDesc().isBranch()) {
374374 bool isCond = false;
375375 unsigned Bits = 0;
376376 unsigned Scale = 1;
422422 // Basic size info comes from the TSFlags field.
423423 unsigned Bits = 0;
424424 unsigned Scale = 1;
425 unsigned TSFlags = I->getDesc()->TSFlags;
425 unsigned TSFlags = I->getDesc().TSFlags;
426426 switch (TSFlags & ARMII::AddrModeMask) {
427427 default:
428428 // Constant pool entries can reach anything.
6262 return true;
6363 case ARM::MOVr:
6464 case ARM::tMOVr:
65 assert(MI.getDesc()->getNumOperands() >= 2 &&
65 assert(MI.getDesc().getNumOperands() >= 2 &&
6666 MI.getOperand(0).isRegister() &&
6767 MI.getOperand(1).isRegister() &&
6868 "Invalid ARM MOV instruction");
179179 return NULL;
180180
181181 MachineInstr *MI = MBBI;
182 unsigned TSFlags = MI->getDesc()->TSFlags;
182 unsigned TSFlags = MI->getDesc().TSFlags;
183183 bool isPre = false;
184184 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
185185 default: return NULL;
199199 MachineInstr *UpdateMI = NULL;
200200 MachineInstr *MemMI = NULL;
201201 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
202 const TargetInstrDescriptor *TID = MI->getDesc();
203 unsigned NumOps = TID->getNumOperands();
204 bool isLoad = TID->isSimpleLoad();
202 const TargetInstrDesc &TID = MI->getDesc();
203 unsigned NumOps = TID.getNumOperands();
204 bool isLoad = TID.isSimpleLoad();
205205 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
206206 const MachineOperand &Base = MI->getOperand(2);
207207 const MachineOperand &Offset = MI->getOperand(NumOps-3);
836836
837837 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
838838 std::vector &Pred) const {
839 const TargetInstrDescriptor *TID = MI->getDesc();
840 if (!TID->getImplicitDefs() && !TID->hasOptionalDef())
839 const TargetInstrDesc &TID = MI->getDesc();
840 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
841841 return false;
842842
843843 bool Found = false;
869869 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
870870
871871 // Basic size info comes from the TSFlags field.
872 const TargetInstrDescriptor *TID = MI->getDesc();
873 unsigned TSFlags = TID->TSFlags;
872 const TargetInstrDesc &TID = MI->getDesc();
873 unsigned TSFlags = TID.TSFlags;
874874
875875 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
876876 default:
896896 case ARM::tBR_JTr: {
897897 // These are jumptable branches, i.e. a branch followed by an inlined
898898 // jumptable. The size is 4 + 4 * number of entries.
899 unsigned NumOps = TID->getNumOperands();
899 unsigned NumOps = TID.getNumOperands();
900900 MachineOperand JTOP =
901 MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
901 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
902902 unsigned JTI = JTOP.getIndex();
903903 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
904904 const std::vector &JT = MJTI->getJumpTables();
598598 unsigned Base = MBBI->getOperand(1).getReg();
599599 unsigned PredReg = 0;
600600 ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
601 const TargetInstrDescriptor *TID = MBBI->getDesc();
602 unsigned OffField = MBBI->getOperand(TID->getNumOperands()-3).getImm();
601 unsigned NumOperands = MBBI->getDesc().getNumOperands();
602 unsigned OffField = MBBI->getOperand(NumOperands-3).getImm();
603603 int Offset = isAM2
604604 ? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
605605 if (isAM2) {
580580 }
581581
582582 unsigned Opcode = MI.getOpcode();
583 const TargetInstrDescriptor &Desc = *MI.getDesc();
583 const TargetInstrDesc &Desc = MI.getDesc();
584584 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
585585 bool isSub = false;
586586
10351035 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
10361036 if (I->getOperand(i).isFrameIndex()) {
10371037 unsigned Opcode = I->getOpcode();
1038 const TargetInstrDescriptor &Desc = TII.get(Opcode);
1038 const TargetInstrDesc &Desc = TII.get(Opcode);
10391039 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
10401040 if (AddrMode == ARMII::AddrMode3) {
10411041 Limit = (1 << 8) - 1;
5858 {
5959 bool Changed = false;
6060 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
61 if (I->getDesc()->hasDelaySlot()) {
61 if (I->getDesc().hasDelaySlot()) {
6262 MachineBasicBlock::iterator J = I;
6363 ++J;
6464 BuildMI(MBB, J, TII->get(Mips::NOP));
174174 // If there is only one terminator instruction, process it.
175175 unsigned LastOpc = LastInst->getOpcode();
176176 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
177 if (!LastInst->getDesc()->isBranch())
177 if (!LastInst->getDesc().isBranch())
178178 return true;
179179
180180 // Unconditional branch
258258 } else {
259259 // Conditional branch.
260260 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
261 const TargetInstrDescriptor &TID = get(Opc);
261 const TargetInstrDesc &TID = get(Opc);
262262
263263 if (TID.getNumOperands() == 3)
264264 BuildMI(&MBB, TID).addReg(Cond[1].getReg())
274274
275275 // Two-way Conditional branch.
276276 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
277 const TargetInstrDescriptor &TID = get(Opc);
277 const TargetInstrDesc &TID = get(Opc);
278278
279279 if (TID.getNumOperands() == 3)
280 BuildMI(&MBB, TID).addReg(Cond[1].getReg())
281 .addReg(Cond[2].getReg())
280 BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
282281 .addMBB(TBB);
283282 else
284 BuildMI(&MBB, TID).addReg(Cond[1].getReg())
285 .addMBB(TBB);
283 BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
286284
287285 BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
288286 return 2;
6969 }
7070 Opcode -= ISD::BUILTIN_OP_END;
7171
72 const TargetInstrDescriptor &TID = TII.get(Opcode);
72 const TargetInstrDesc &TID = TII.get(Opcode);
7373
7474 isLoad = TID.isSimpleLoad();
7575 isStore = TID.mayStore();
261261
262262 // Find all return blocks, outputting a restore in each epilog.
263263 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
264 if (!BB->empty() && BB->back().getDesc()->isReturn()) {
264 if (!BB->empty() && BB->back().getDesc().isReturn()) {
265265 IP = BB->end(); --IP;
266266
267267 // Skip over all terminator instructions, which are part of the return
268268 // sequence.
269269 MachineBasicBlock::iterator I2 = IP;
270 while (I2 != BB->begin() && (--I2)->getDesc()->isTerminator())
270 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
271271 IP = I2;
272272
273273 // Emit: MTVRSAVE InVRSave
539539 // epilog blocks.
540540 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
541541 // If last instruction is a return instruction, add an epilogue
542 if (!I->empty() && I->back().getDesc()->isReturn()) {
542 if (!I->empty() && I->back().getDesc().isReturn()) {
543543 bool FoundIt = false;
544544 for (MBBI = I->end(); MBBI != I->begin(); ) {
545545 --MBBI;
6464 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
6565 bool Changed = false;
6666 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
67 if (I->getDesc()->hasDelaySlot()) {
67 if (I->getDesc().hasDelaySlot()) {
6868 MachineBasicBlock::iterator J = I;
6969 ++J;
7070 BuildMI(MBB, J, TII->get(SP::NOP));
1717
1818 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
1919 /// dest operand. Returns -1 if there isn't one.
20 int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
20 int TargetInstrDesc::findTiedToSrcOperand(unsigned OpNum) const {
2121 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2222 if (i == OpNum)
2323 continue;
2828 }
2929
3030
31 TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
31 TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
3232 unsigned numOpcodes)
33 : desc(Desc), NumOpcodes(numOpcodes) {
33 : Descriptors(Desc), NumOpcodes(numOpcodes) {
3434 }
3535
3636 TargetInstrInfo::~TargetInstrInfo() {
3737 }
3838
3939 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
40 const TargetInstrDescriptor *TID = MI->getDesc();
41 if (!TID->isTerminator()) return false;
40 const TargetInstrDesc &TID = MI->getDesc();
41 if (!TID.isTerminator()) return false;
4242
4343 // Conditional branch is a special case.
44 if (TID->isBranch() && !TID->isBarrier())
44 if (TID.isBranch() && !TID.isBarrier())
4545 return true;
46 if (!TID->isPredicable())
46 if (!TID.isPredicable())
4747 return true;
4848 return !isPredicated(MI);
4949 }
5959 }
6060
6161 void emitInstruction(const MachineInstr &MI,
62 const TargetInstrDescriptor *Desc);
62 const TargetInstrDesc *Desc);
6363
6464 private:
6565 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
114114 MCE.StartMachineBasicBlock(MBB);
115115 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
116116 I != E; ++I) {
117 const TargetInstrDescriptor *Desc = I->getDesc();
118 emitInstruction(*I, Desc);
117 const TargetInstrDesc &Desc = I->getDesc();
118 emitInstruction(*I, &Desc);
119119 // MOVPC32r is basically a call plus a pop instruction.
120 if (Desc->Opcode == X86::MOVPC32r)
120 if (Desc.getOpcode() == X86::MOVPC32r)
121121 emitInstruction(*I, &II->get(X86::POP32r));
122122 NumEmitted++; // Keep track of the # of mi's emitted
123123 }
393393 }
394394 }
395395
396 static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
396 static unsigned sizeOfImm(const TargetInstrDesc *Desc) {
397397 switch (Desc->TSFlags & X86II::ImmMask) {
398398 case X86II::Imm8: return 1;
399399 case X86II::Imm16: return 2;
435435 /// size, and 3) use of X86-64 extended registers.
436436 unsigned Emitter::determineREX(const MachineInstr &MI) {
437437 unsigned REX = 0;
438 const TargetInstrDescriptor *Desc = MI.getDesc();
438 const TargetInstrDesc &Desc = MI.getDesc();
439439
440440 // Pseudo instructions do not need REX prefix byte.
441 if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
441 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
442442 return 0;
443 if (Desc->TSFlags & X86II::REX_W)
443 if (Desc.TSFlags & X86II::REX_W)
444444 REX |= 1 << 3;
445445
446 unsigned NumOps = Desc->getNumOperands();
446 unsigned NumOps = Desc.getNumOperands();
447447 if (NumOps) {
448448 bool isTwoAddr = NumOps > 1 &&
449 Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
449 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
450450
451451 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
452452 unsigned i = isTwoAddr ? 1 : 0;
459459 }
460460 }
461461
462 switch (Desc->TSFlags & X86II::FormMask) {
462 switch (Desc.TSFlags & X86II::FormMask) {
463463 case X86II::MRMInitReg:
464464 if (isX86_64ExtendedReg(MI.getOperand(0)))
465465 REX |= (1 << 0) | (1 << 2);
527527 }
528528
529529 void Emitter::emitInstruction(const MachineInstr &MI,
530 const TargetInstrDescriptor *Desc) {
530 const TargetInstrDesc *Desc) {
531531 unsigned Opcode = Desc->Opcode;
532532
533533 // Emit the repeat opcode prefix as needed.
204204
205205 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
206206 MachineInstr *MI = I;
207 unsigned Flags = MI->getDesc()->TSFlags;
207 unsigned Flags = MI->getDesc().TSFlags;
208208 if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
209209 continue; // Efficiently ignore non-fp insts!
210210
596596 ///
597597 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
598598 MachineInstr *MI = I;
599 unsigned NumOps = MI->getDesc()->getNumOperands();
599 unsigned NumOps = MI->getDesc().getNumOperands();
600600 assert((NumOps == 5 || NumOps == 1) &&
601601 "Can only handle fst* & ftst instructions!");
602602
656656 ///
657657 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
658658 MachineInstr *MI = I;
659 unsigned NumOps = MI->getDesc()->getNumOperands();
659 unsigned NumOps = MI->getDesc().getNumOperands();
660660 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
661661
662662 // Is this the last use of the source register?
765765 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
766766 MachineInstr *MI = I;
767767
768 unsigned NumOperands = MI->getDesc()->getNumOperands();
768 unsigned NumOperands = MI->getDesc().getNumOperands();
769769 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
770770 unsigned Dest = getFPReg(MI->getOperand(0));
771771 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
863863 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
864864 MachineInstr *MI = I;
865865
866 unsigned NumOperands = MI->getDesc()->getNumOperands();
866 unsigned NumOperands = MI->getDesc().getNumOperands();
867867 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
868868 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
869869 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
12421242 }
12431243
12441244 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1245 const TargetInstrDescriptor *TID = MI->getDesc();
1246 if (!TID->isTerminator()) return false;
1245 const TargetInstrDesc &TID = MI->getDesc();
1246 if (!TID.isTerminator()) return false;
12471247
12481248 // Conditional branch is a special case.
1249 if (TID->isBranch() && !TID->isBarrier())
1249 if (TID.isBranch() && !TID.isBarrier())
12501250 return true;
1251 if (!TID->isPredicable())
1251 if (!TID.isPredicable())
12521252 return true;
12531253 return !isPredicated(MI);
12541254 }
12751275
12761276 // If there is only one terminator instruction, process it.
12771277 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
1278 if (!LastInst->getDesc()->isBranch())
1278 if (!LastInst->getDesc().isBranch())
12791279 return true;
12801280
12811281 // If the block ends with a branch there are 3 possibilities:
16391639 MIB.addImm(1).addReg(0).addImm(0);
16401640
16411641 // Loop over the rest of the ri operands, converting them over.
1642 unsigned NumOps = MI->getDesc()->getNumOperands()-2;
1642 unsigned NumOps = MI->getDesc().getNumOperands()-2;
16431643 for (unsigned i = 0; i != NumOps; ++i) {
16441644 MachineOperand &MO = MI->getOperand(i+2);
16451645 MIB = X86InstrAddOperand(MIB, MO);
16911691 SmallVector &MOs) const {
16921692 const DenseMap *OpcodeTablePtr = NULL;
16931693 bool isTwoAddrFold = false;
1694 unsigned NumOps = MI->getDesc()->getNumOperands();
1694 unsigned NumOps = MI->getDesc().getNumOperands();
16951695 bool isTwoAddr = NumOps > 1 &&
1696 MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
1696 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
16971697
16981698 MachineInstr *NewMI = NULL;
16991699 // Folding a memory location into the two-address part of a two-address
17971797 return NULL;
17981798
17991799 SmallVector MOs;
1800 unsigned NumOps = LoadMI->getDesc()->getNumOperands();
1800 unsigned NumOps = LoadMI->getDesc().getNumOperands();
18011801 for (unsigned i = NumOps - 4; i != NumOps; ++i)
18021802 MOs.push_back(LoadMI->getOperand(i));
18031803 return foldMemoryOperand(MI, Ops[0], MOs);
18251825
18261826 unsigned OpNum = Ops[0];
18271827 unsigned Opc = MI->getOpcode();
1828 unsigned NumOps = MI->getDesc()->getNumOperands();
1828 unsigned NumOps = MI->getDesc().getNumOperands();
18291829 bool isTwoAddr = NumOps > 1 &&
1830 MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
1830 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
18311831
18321832 // Folding a memory location into the two-address part of a two-address
18331833 // instruction is different than folding it other places. It requires
18791879 return false;
18801880 UnfoldStore &= FoldedStore;
18811881
1882 const TargetInstrDescriptor &TID = get(Opc);
1882 const TargetInstrDesc &TID = get(Opc);
18831883 const TargetOperandInfo &TOI = TID.OpInfo[Index];
18841884 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
18851885 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
19781978 unsigned Index = I->second.second & 0xf;
19791979 bool FoldedLoad = I->second.second & (1 << 4);
19801980 bool FoldedStore = I->second.second & (1 << 5);
1981 const TargetInstrDescriptor &TID = get(Opc);
1981 const TargetInstrDesc &TID = get(Opc);
19821982 const TargetOperandInfo &TOI = TID.OpInfo[Index];
19831983 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
19841984 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
363363 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
364364 // specified machine instruction.
365365 //
366 unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const {
366 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
367367 return TID->TSFlags >> X86II::OpcodeShift;
368368 }
369369 unsigned char getBaseOpcodeFor(unsigned Opcode) const {
728728 MachineBasicBlock::iterator PI = prior(MBBI);
729729 unsigned Opc = PI->getOpcode();
730730 if (Opc != X86::POP32r && Opc != X86::POP64r &&
731 !PI->getDesc()->isTerminator())
731 !PI->getDesc().isTerminator())
732732 break;
733733 --MBBI;
734734 }
260260 // Emit all of the operand info records.
261261 EmitOperandInfo(OS, OperandInfoIDs);
262262
263 // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
263 // Emit all of the TargetInstrDesc records in their ENUM ordering.
264264 //
265 OS << "\nstatic const TargetInstrDescriptor " << TargetName
265 OS << "\nstatic const TargetInstrDesc " << TargetName
266266 << "Insts[] = {\n";
267267 std::vector NumberedInstructions;
268268 Target.getInstructionsByEnumValue(NumberedInstructions);