llvm.org GIT mirror llvm / 746ad69
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
38 changed file(s) with 182 addition(s) and 111 deletion(s). Raw diff Collapse all Expand all
327327 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
328328 MachineBasicBlock::iterator MI,
329329 unsigned SrcReg, bool isKill, int FrameIndex,
330 const TargetRegisterClass *RC) const {
330 const TargetRegisterClass *RC,
331 const TargetRegisterInfo *TRI) const {
331332 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
332333 }
333334
338339 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
339340 MachineBasicBlock::iterator MI,
340341 unsigned DestReg, int FrameIndex,
341 const TargetRegisterClass *RC) const {
342 const TargetRegisterClass *RC,
343 const TargetRegisterInfo *TRI) const {
342344 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
343345 }
344346
10601060 // Add spill.
10611061
10621062 SS = CreateSpillStackSlot(CurrLI->reg, RC);
1063 TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
1063 TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC,
1064 TRI);
10641065 SpillMI = prior(SpillPt);
10651066 SpillIndex = LIs->InsertMachineInstrInMaps(SpillMI);
10661067 }
10961097 }
10971098 // Add spill.
10981099 SS = CreateSpillStackSlot(CurrLI->reg, RC);
1099 TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg, false, SS, RC);
1100 TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg, false, SS, RC,
1101 TRI);
11001102 SpillMI = prior(SpillPt);
11011103 SpillIndex = LIs->InsertMachineInstrInMaps(SpillMI);
11021104 }
11151117 RestoreIndex = LIs->getInstructionIndex(RestorePt);
11161118 FoldedRestore = true;
11171119 } else {
1118 TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC);
1120 TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC, TRI);
11191121 MachineInstr *LoadMI = prior(RestorePt);
11201122 RestoreIndex = LIs->InsertMachineInstrInMaps(LoadMI);
11211123 }
288288 return;
289289
290290 const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
291 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
291292 MachineBasicBlock::iterator I;
292293
293294 if (! ShrinkWrapThisFunction) {
301302
302303 // Insert the spill to the stack frame.
303304 TII.storeRegToStackSlot(*EntryBlock, I, CSI[i].getReg(), true,
304 CSI[i].getFrameIdx(), CSI[i].getRegClass());
305 CSI[i].getFrameIdx(), CSI[i].getRegClass(),TRI);
305306 }
306307 }
307308
327328 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
328329 TII.loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
329330 CSI[i].getFrameIdx(),
330 CSI[i].getRegClass());
331 CSI[i].getRegClass(), TRI);
331332 assert(I != MBB->begin() &&
332333 "loadRegFromStackSlot didn't insert any code!");
333334 // Insert in reverse order. loadRegFromStackSlot can insert
374375 TII.storeRegToStackSlot(*MBB, I, blockCSI[i].getReg(),
375376 true,
376377 blockCSI[i].getFrameIdx(),
377 blockCSI[i].getRegClass());
378 blockCSI[i].getRegClass(), TRI);
378379 }
379380 }
380381
422423 for (unsigned i = 0, e = blockCSI.size(); i != e; ++i) {
423424 TII.loadRegFromStackSlot(*MBB, I, blockCSI[i].getReg(),
424425 blockCSI[i].getFrameIdx(),
425 blockCSI[i].getRegClass());
426 blockCSI[i].getRegClass(), TRI);
426427 assert(I != MBB->begin() &&
427428 "loadRegFromStackSlot didn't insert any code!");
428429 // Insert in reverse order. loadRegFromStackSlot can insert
280280 // happen if it is a move to a physical register), then the spill
281281 // instruction is not a kill.
282282 bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg));
283 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
283 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC, TRI);
284284 ++NumStores; // Update statistics
285285 }
286286
475475 << TRI->getName(PhysReg) << "\n");
476476
477477 // Add move instruction(s)
478 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
478 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC, TRI);
479479 ++NumLoads; // Update statistics
480480
481481 MF->getRegInfo().setPhysRegUsed(PhysReg);
296296 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
297297 int FrameIndex = getStackSpaceFor(VirtReg, RC);
298298 DEBUG(dbgs() << " to stack slot #" << FrameIndex);
299 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC);
299 TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC, TRI);
300300 ++NumStores; // Update statistics
301301 }
302302
542542 << TRI->getName(PhysReg) << "\n");
543543
544544 // Add move instruction(s)
545 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
545 TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC, TRI);
546546 ++NumLoads; // Update statistics
547547
548548 MF->getRegInfo().setPhysRegUsed(PhysReg);
342342 // Spill the scavenged register before I.
343343 assert(ScavengingFrameIndex >= 0 &&
344344 "Cannot scavenge register without an emergency spill slot!");
345 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
345 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
346346 MachineBasicBlock::iterator II = prior(I);
347347 TRI->eliminateFrameIndex(II, SPAdj, NULL, this);
348348
349349 // Restore the scavenged register before its use (or first terminator).
350 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC);
350 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
351351 II = prior(UseMI);
352352 TRI->eliminateFrameIndex(II, SPAdj, NULL, this);
353353 }
5050 MachineFrameInfo *mfi;
5151 MachineRegisterInfo *mri;
5252 const TargetInstrInfo *tii;
53 const TargetRegisterInfo *tri;
5354 VirtRegMap *vrm;
5455
5556 /// Construct a spiller base.
5960 mfi = mf->getFrameInfo();
6061 mri = &mf->getRegInfo();
6162 tii = mf->getTarget().getInstrInfo();
63 tri = mf->getTarget().getRegisterInfo();
6264 }
6365
6466 /// Add spill ranges for every use/def of the live interval, inserting loads
128130 // Insert reload if necessary.
129131 MachineBasicBlock::iterator miItr(mi);
130132 if (hasUse) {
131 tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc);
133 tii->loadRegFromStackSlot(*mi->getParent(), miItr, newVReg, ss, trc,
134 tri);
132135 MachineInstr *loadInstr(prior(miItr));
133136 SlotIndex loadIndex =
134137 lis->InsertMachineInstrInMaps(loadInstr).getDefIndex();
142145 // Insert store if necessary.
143146 if (hasDef) {
144147 tii->storeRegToStackSlot(*mi->getParent(), llvm::next(miItr), newVReg,
145 true, ss, trc);
148 true, ss, trc, tri);
146149 MachineInstr *storeInstr(llvm::next(miItr));
147150 SlotIndex storeIndex =
148151 lis->InsertMachineInstrInMaps(storeInstr).getDefIndex();
906906 TRI, VRM);
907907 } else {
908908 TII->loadRegFromStackSlot(*MBB, InsertLoc, NewPhysReg,
909 NewOp.StackSlotOrReMat, AliasRC);
909 NewOp.StackSlotOrReMat, AliasRC, TRI);
910910 MachineInstr *LoadMI = prior(InsertLoc);
911911 VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI);
912912 // Any stores to this stack slot are not dead anymore.
12641264 ComputeReloadLoc(MII, MBB->begin(), PhysReg, TRI, false, SS, TII, MF);
12651265
12661266 // Load from SS to the spare physical register.
1267 TII->loadRegFromStackSlot(*MBB, MII, PhysReg, SS, RC);
1267 TII->loadRegFromStackSlot(*MBB, MII, PhysReg, SS, RC, TRI);
12681268 // This invalidates Phys.
12691269 Spills.ClobberPhysReg(PhysReg);
12701270 // Remember it's available.
13071307 } while (FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, *VRM));
13081308
13091309 // Store the value back into SS.
1310 TII->storeRegToStackSlot(*MBB, NextMII, PhysReg, true, SS, RC);
1310 TII->storeRegToStackSlot(*MBB, NextMII, PhysReg, true, SS, RC, TRI);
13111311 MachineInstr *StoreMI = prior(NextMII);
13121312 VRM->addSpillSlotUse(SS, StoreMI);
13131313 VRM->virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
15221522 VRM->virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
15231523 // Insert new def MI and spill MI.
15241524 const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
1525 TII->storeRegToStackSlot(*MBB, &MI, NewReg, true, SS, RC);
1525 TII->storeRegToStackSlot(*MBB, &MI, NewReg, true, SS, RC, TRI);
15261526 MII = prior(MII);
15271527 MachineInstr *StoreMI = MII;
15281528 VRM->addSpillSlotUse(SS, StoreMI);
15651565 std::vector &KillOps) {
15661566
15671567 MachineBasicBlock::iterator oldNextMII = llvm::next(MII);
1568 TII->storeRegToStackSlot(*MBB, llvm::next(MII), PhysReg, true, StackSlot, RC);
1568 TII->storeRegToStackSlot(*MBB, llvm::next(MII), PhysReg, true, StackSlot, RC,
1569 TRI);
15691570 MachineInstr *StoreMI = prior(oldNextMII);
15701571 VRM->addSpillSlotUse(StackSlot, StoreMI);
15711572 DEBUG(dbgs() << "Store:\t" << *StoreMI);
17081709 if (UsedSS.count(SS))
17091710 llvm_unreachable("Need to spill more than one physical registers!");
17101711 UsedSS.insert(SS);
1711 TII->storeRegToStackSlot(*MBB, MII, PhysReg, true, SS, RC);
1712 TII->storeRegToStackSlot(*MBB, MII, PhysReg, true, SS, RC, TRI);
17121713 MachineInstr *StoreMI = prior(MII);
17131714 VRM->addSpillSlotUse(SS, StoreMI);
17141715
17171718 ComputeReloadLoc(llvm::next(MII), MBB->begin(), PhysReg, TRI, false, SS,
17181719 TII, *MBB->getParent());
17191720
1720 TII->loadRegFromStackSlot(*MBB, InsertLoc, PhysReg, SS, RC);
1721 TII->loadRegFromStackSlot(*MBB, InsertLoc, PhysReg, SS, RC, TRI);
17211722
17221723 MachineInstr *LoadMI = prior(InsertLoc);
17231724 VRM->addSpillSlotUse(SS, LoadMI);
18201821 ReMaterialize(*MBB, InsertLoc, Phys, VirtReg, TII, TRI, *VRM);
18211822 } else {
18221823 const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
1823 TII->loadRegFromStackSlot(*MBB, InsertLoc, Phys, SSorRMId, RC);
1824 TII->loadRegFromStackSlot(*MBB, InsertLoc, Phys, SSorRMId, RC, TRI);
18241825 MachineInstr *LoadMI = prior(InsertLoc);
18251826 VRM->addSpillSlotUse(SSorRMId, LoadMI);
18261827 ++NumLoads;
18561857 int StackSlot = VRM->getStackSlot(VirtReg);
18571858 MachineBasicBlock::iterator oldNextMII = llvm::next(MII);
18581859 TII->storeRegToStackSlot(*MBB, llvm::next(MII), Phys, isKill, StackSlot,
1859 RC);
1860 RC, TRI);
18601861 MachineInstr *StoreMI = prior(oldNextMII);
18611862 VRM->addSpillSlotUse(StackSlot, StoreMI);
18621863 DEBUG(dbgs() << "Store:\t" << *StoreMI);
21822183 ReMaterialize(*MBB, InsertLoc, PhysReg, VirtReg, TII, TRI, *VRM);
21832184 } else {
21842185 const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
2185 TII->loadRegFromStackSlot(*MBB, InsertLoc, PhysReg, SSorRMId, RC);
2186 TII->loadRegFromStackSlot(*MBB, InsertLoc, PhysReg, SSorRMId, RC,TRI);
21862187 MachineInstr *LoadMI = prior(InsertLoc);
21872188 VRM->addSpillSlotUse(SSorRMId, LoadMI);
21882189 ++NumLoads;
727727 void ARMBaseInstrInfo::
728728 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
729729 unsigned SrcReg, bool isKill, int FI,
730 const TargetRegisterClass *RC) const {
730 const TargetRegisterClass *RC,
731 const TargetRegisterInfo *TRI) const {
731732 DebugLoc DL;
732733 if (I != MBB.end()) DL = I->getDebugLoc();
733734 MachineFunction &MF = *MBB.getParent();
786787 void ARMBaseInstrInfo::
787788 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
788789 unsigned DestReg, int FI,
789 const TargetRegisterClass *RC) const {
790 const TargetRegisterClass *RC,
791 const TargetRegisterInfo *TRI) const {
790792 DebugLoc DL;
791793 if (I != MBB.end()) DL = I->getDebugLoc();
792794 MachineFunction &MF = *MBB.getParent();
261261 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
262262 MachineBasicBlock::iterator MBBI,
263263 unsigned SrcReg, bool isKill, int FrameIndex,
264 const TargetRegisterClass *RC) const;
264 const TargetRegisterClass *RC,
265 const TargetRegisterInfo *TRI) const;
265266
266267 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
267268 MachineBasicBlock::iterator MBBI,
268269 unsigned DestReg, int FrameIndex,
269 const TargetRegisterClass *RC) const;
270 const TargetRegisterClass *RC,
271 const TargetRegisterInfo *TRI) const;
270272
271273 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
272274 int FrameIx,
9696 void Thumb1InstrInfo::
9797 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
9898 unsigned SrcReg, bool isKill, int FI,
99 const TargetRegisterClass *RC) const {
100 DebugLoc DL;
101 if (I != MBB.end()) DL = I->getDebugLoc();
102
99 const TargetRegisterClass *RC,
100 const TargetRegisterInfo *TRI) const {
103101 assert((RC == ARM::tGPRRegisterClass ||
104102 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
105103 isARMLowRegister(SrcReg))) && "Unknown regclass!");
107105 if (RC == ARM::tGPRRegisterClass ||
108106 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
109107 isARMLowRegister(SrcReg))) {
108 DebugLoc DL;
109 if (I != MBB.end()) DL = I->getDebugLoc();
110
110111 MachineFunction &MF = *MBB.getParent();
111112 MachineFrameInfo &MFI = *MF.getFrameInfo();
112113 MachineMemOperand *MMO =
123124 void Thumb1InstrInfo::
124125 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
125126 unsigned DestReg, int FI,
126 const TargetRegisterClass *RC) const {
127 DebugLoc DL;
128 if (I != MBB.end()) DL = I->getDebugLoc();
129
127 const TargetRegisterClass *RC,
128 const TargetRegisterInfo *TRI) const {
130129 assert((RC == ARM::tGPRRegisterClass ||
131130 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
132131 isARMLowRegister(DestReg))) && "Unknown regclass!");
134133 if (RC == ARM::tGPRRegisterClass ||
135134 (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
136135 isARMLowRegister(DestReg))) {
136 DebugLoc DL;
137 if (I != MBB.end()) DL = I->getDebugLoc();
138
137139 MachineFunction &MF = *MBB.getParent();
138140 MachineFrameInfo &MFI = *MF.getFrameInfo();
139141 MachineMemOperand *MMO =
5151 void storeRegToStackSlot(MachineBasicBlock &MBB,
5252 MachineBasicBlock::iterator MBBI,
5353 unsigned SrcReg, bool isKill, int FrameIndex,
54 const TargetRegisterClass *RC) const;
54 const TargetRegisterClass *RC,
55 const TargetRegisterInfo *TRI) const;
5556
5657 void loadRegFromStackSlot(MachineBasicBlock &MBB,
5758 MachineBasicBlock::iterator MBBI,
5859 unsigned DestReg, int FrameIndex,
59 const TargetRegisterClass *RC) const;
60 const TargetRegisterClass *RC,
61 const TargetRegisterInfo *TRI) const;
6062
6163 bool canFoldMemoryOperand(const MachineInstr *MI,
6264 const SmallVectorImpl &Ops) const;
6868 void Thumb2InstrInfo::
6969 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
7070 unsigned SrcReg, bool isKill, int FI,
71 const TargetRegisterClass *RC) const {
72 DebugLoc DL;
73 if (I != MBB.end()) DL = I->getDebugLoc();
74
71 const TargetRegisterClass *RC,
72 const TargetRegisterInfo *TRI) const {
7573 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) {
74 DebugLoc DL;
75 if (I != MBB.end()) DL = I->getDebugLoc();
76
7677 MachineFunction &MF = *MBB.getParent();
7778 MachineFrameInfo &MFI = *MF.getFrameInfo();
7879 MachineMemOperand *MMO =
8687 return;
8788 }
8889
89 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC);
90 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
9091 }
9192
9293 void Thumb2InstrInfo::
9394 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
9495 unsigned DestReg, int FI,
95 const TargetRegisterClass *RC) const {
96 DebugLoc DL;
97 if (I != MBB.end()) DL = I->getDebugLoc();
98
96 const TargetRegisterClass *RC,
97 const TargetRegisterInfo *TRI) const {
9998 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) {
99 DebugLoc DL;
100 if (I != MBB.end()) DL = I->getDebugLoc();
101
100102 MachineFunction &MF = *MBB.getParent();
101103 MachineFrameInfo &MFI = *MF.getFrameInfo();
102104 MachineMemOperand *MMO =
109111 return;
110112 }
111113
112 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC);
114 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
113115 }
114116
115117 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
3939 void storeRegToStackSlot(MachineBasicBlock &MBB,
4040 MachineBasicBlock::iterator MBBI,
4141 unsigned SrcReg, bool isKill, int FrameIndex,
42 const TargetRegisterClass *RC) const;
42 const TargetRegisterClass *RC,
43 const TargetRegisterInfo *TRI) const;
4344
4445 void loadRegFromStackSlot(MachineBasicBlock &MBB,
4546 MachineBasicBlock::iterator MBBI,
4647 unsigned DestReg, int FrameIndex,
47 const TargetRegisterClass *RC) const;
48 const TargetRegisterClass *RC,
49 const TargetRegisterInfo *TRI) const;
4850
4951 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
5052 /// such, whenever a client has an instance of instruction info, it should
179179 AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
180180 MachineBasicBlock::iterator MI,
181181 unsigned SrcReg, bool isKill, int FrameIdx,
182 const TargetRegisterClass *RC) const {
182 const TargetRegisterClass *RC,
183 const TargetRegisterInfo *TRI) const {
183184 //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
184185 // << FrameIdx << "\n";
185186 //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
207208 AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
208209 MachineBasicBlock::iterator MI,
209210 unsigned DestReg, int FrameIdx,
210 const TargetRegisterClass *RC) const {
211 const TargetRegisterClass *RC,
212 const TargetRegisterInfo *TRI) const {
211213 //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
212214 // << FrameIdx << "\n";
213215 DebugLoc DL;
5151 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
5252 MachineBasicBlock::iterator MBBI,
5353 unsigned SrcReg, bool isKill, int FrameIndex,
54 const TargetRegisterClass *RC) const;
54 const TargetRegisterClass *RC,
55 const TargetRegisterInfo *TRI) const;
5556
5657 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
5758 MachineBasicBlock::iterator MBBI,
5859 unsigned DestReg, int FrameIndex,
59 const TargetRegisterClass *RC) const;
60 const TargetRegisterClass *RC,
61 const TargetRegisterInfo *TRI) const;
6062
6163 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
6264 MachineInstr* MI,
195195 unsigned SrcReg,
196196 bool isKill,
197197 int FI,
198 const TargetRegisterClass *RC) const {
198 const TargetRegisterClass *RC,
199 const TargetRegisterInfo *TRI) const {
199200 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
200201
201202 if (inClass(BF::DPRegClass, SrcReg, RC)) {
241242 MachineBasicBlock::iterator I,
242243 unsigned DestReg,
243244 int FI,
244 const TargetRegisterClass *RC) const {
245 const TargetRegisterClass *RC,
246 const TargetRegisterInfo *TRI) const {
245247 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
246248 if (inClass(BF::DPRegClass, DestReg, RC)) {
247249 BuildMI(MBB, I, DL, get(BF::LOAD32fi), DestReg)
5555 MachineBasicBlock::iterator MBBI,
5656 unsigned SrcReg, bool isKill,
5757 int FrameIndex,
58 const TargetRegisterClass *RC) const;
58 const TargetRegisterClass *RC,
59 const TargetRegisterInfo *TRI) const;
5960
6061 virtual void storeRegToAddr(MachineFunction &MF,
6162 unsigned SrcReg, bool isKill,
6667 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
6768 MachineBasicBlock::iterator MBBI,
6869 unsigned DestReg, int FrameIndex,
69 const TargetRegisterClass *RC) const;
70 const TargetRegisterClass *RC,
71 const TargetRegisterInfo *TRI) const;
7072
7173 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
7274 SmallVectorImpl &Addr,
290290
291291 void
292292 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
293 MachineBasicBlock::iterator MI,
294 unsigned SrcReg, bool isKill, int FrameIdx,
295 const TargetRegisterClass *RC) const
293 MachineBasicBlock::iterator MI,
294 unsigned SrcReg, bool isKill, int FrameIdx,
295 const TargetRegisterClass *RC,
296 const TargetRegisterInfo *TRI) const
296297 {
297298 unsigned opc;
298299 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
324325
325326 void
326327 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
327 MachineBasicBlock::iterator MI,
328 unsigned DestReg, int FrameIdx,
329 const TargetRegisterClass *RC) const
328 MachineBasicBlock::iterator MI,
329 unsigned DestReg, int FrameIdx,
330 const TargetRegisterClass *RC,
331 const TargetRegisterInfo *TRI) const
330332 {
331333 unsigned opc;
332334 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
6565 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
6666 MachineBasicBlock::iterator MBBI,
6767 unsigned SrcReg, bool isKill, int FrameIndex,
68 const TargetRegisterClass *RC) const;
68 const TargetRegisterClass *RC,
69 const TargetRegisterInfo *TRI) const;
6970
7071 //! Load a register from a stack slot, based on its register class.
7172 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
7273 MachineBasicBlock::iterator MBBI,
7374 unsigned DestReg, int FrameIndex,
74 const TargetRegisterClass *RC) const;
75 const TargetRegisterClass *RC,
76 const TargetRegisterInfo *TRI) const;
7577
7678 //! Return true if the specified load or store can be folded
7779 virtual
123123 void MBlazeInstrInfo::
124124 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
125125 unsigned SrcReg, bool isKill, int FI,
126 const TargetRegisterClass *RC) const {
126 const TargetRegisterClass *RC,
127 const TargetRegisterInfo *TRI) const {
127128 DebugLoc DL;
128129 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill))
129130 .addImm(0).addFrameIndex(FI);
132133 void MBlazeInstrInfo::
133134 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
134135 unsigned DestReg, int FI,
135 const TargetRegisterClass *RC) const {
136 const TargetRegisterClass *RC,
137 const TargetRegisterInfo *TRI) const {
136138 DebugLoc DL;
137139 BuildMI(MBB, I, DL, get(MBlaze::LWI), DestReg)
138140 .addImm(0).addFrameIndex(FI);
206206 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
207207 MachineBasicBlock::iterator MBBI,
208208 unsigned SrcReg, bool isKill, int FrameIndex,
209 const TargetRegisterClass *RC) const;
209 const TargetRegisterClass *RC,
210 const TargetRegisterInfo *TRI) const;
210211
211212 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
212213 MachineBasicBlock::iterator MBBI,
213214 unsigned DestReg, int FrameIndex,
214 const TargetRegisterClass *RC) const;
215 const TargetRegisterClass *RC,
216 const TargetRegisterInfo *TRI) const;
215217
216218 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
217219 MachineInstr* MI,
3131 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3232 MachineBasicBlock::iterator MI,
3333 unsigned SrcReg, bool isKill, int FrameIdx,
34 const TargetRegisterClass *RC) const {
34 const TargetRegisterClass *RC,
35 const TargetRegisterInfo *TRI) const {
3536 DebugLoc DL;
3637 if (MI != MBB.end()) DL = MI->getDebugLoc();
3738 MachineFunction &MF = *MBB.getParent();
5859 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
5960 MachineBasicBlock::iterator MI,
6061 unsigned DestReg, int FrameIdx,
61 const TargetRegisterClass *RC) const{
62 const TargetRegisterClass *RC,
63 const TargetRegisterInfo *TRI) const{
6264 DebugLoc DL;
6365 if (MI != MBB.end()) DL = MI->getDebugLoc();
6466 MachineFunction &MF = *MBB.getParent();
6161 MachineBasicBlock::iterator MI,
6262 unsigned SrcReg, bool isKill,
6363 int FrameIndex,
64 const TargetRegisterClass *RC) const;
64 const TargetRegisterClass *RC,
65 const TargetRegisterInfo *TRI) const;
6566 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
6667 MachineBasicBlock::iterator MI,
6768 unsigned DestReg, int FrameIdx,
68 const TargetRegisterClass *RC) const;
69 const TargetRegisterClass *RC,
70 const TargetRegisterInfo *TRI) const;
6971
7072 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
7173 MachineBasicBlock::iterator MI,
188188 void MipsInstrInfo::
189189 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
190190 unsigned SrcReg, bool isKill, int FI,
191 const TargetRegisterClass *RC) const {
191 const TargetRegisterClass *RC,
192 const TargetRegisterInfo *TRI) const {
192193 DebugLoc DL;
193194 if (I != MBB.end()) DL = I->getDebugLoc();
194195
221222 void MipsInstrInfo::
222223 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
223224 unsigned DestReg, int FI,
224 const TargetRegisterClass *RC) const
225 const TargetRegisterClass *RC,
226 const TargetRegisterInfo *TRI) const
225227 {
226228 DebugLoc DL;
227229 if (I != MBB.end()) DL = I->getDebugLoc();
212212 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
213213 MachineBasicBlock::iterator MBBI,
214214 unsigned SrcReg, bool isKill, int FrameIndex,
215 const TargetRegisterClass *RC) const;
215 const TargetRegisterClass *RC,
216 const TargetRegisterInfo *TRI) const;
216217
217218 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
218219 MachineBasicBlock::iterator MBBI,
219220 unsigned DestReg, int FrameIndex,
220 const TargetRegisterClass *RC) const;
221 const TargetRegisterClass *RC,
222 const TargetRegisterInfo *TRI) const;
221223
222224 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
223225 MachineInstr* MI,
6969 void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
7070 MachineBasicBlock::iterator I,
7171 unsigned SrcReg, bool isKill, int FI,
72 const TargetRegisterClass *RC) const {
72 const TargetRegisterClass *RC,
73 const TargetRegisterInfo *TRI) const {
7374 const PIC16TargetLowering *PTLI = TM.getTargetLowering();
7475 DebugLoc DL;
7576 if (I != MBB.end()) DL = I->getDebugLoc();
111112 void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
112113 MachineBasicBlock::iterator I,
113114 unsigned DestReg, int FI,
114 const TargetRegisterClass *RC) const {
115 const TargetRegisterClass *RC,
116 const TargetRegisterInfo *TRI) const {
115117 const PIC16TargetLowering *PTLI = TM.getTargetLowering();
116118 DebugLoc DL;
117119 if (I != MBB.end()) DL = I->getDebugLoc();
4848 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
4949 MachineBasicBlock::iterator MBBI,
5050 unsigned SrcReg, bool isKill, int FrameIndex,
51 const TargetRegisterClass *RC) const;
51 const TargetRegisterClass *RC,
52 const TargetRegisterInfo *TRI) const;
5253
5354 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
5455 MachineBasicBlock::iterator MBBI,
5556 unsigned DestReg, int FrameIndex,
56 const TargetRegisterClass *RC) const;
57 const TargetRegisterClass *RC,
58 const TargetRegisterInfo *TRI) const;
5759 virtual bool copyRegToReg(MachineBasicBlock &MBB,
5860 MachineBasicBlock::iterator MBBI,
5961 unsigned DestReg, unsigned SrcReg,
517517 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
518518 MachineBasicBlock::iterator MI,
519519 unsigned SrcReg, bool isKill, int FrameIdx,
520 const TargetRegisterClass *RC) const {
520 const TargetRegisterClass *RC,
521 const TargetRegisterInfo *TRI) const {
521522 MachineFunction &MF = *MBB.getParent();
522523 SmallVector NewMIs;
523524
632633 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
633634 MachineBasicBlock::iterator MI,
634635 unsigned DestReg, int FrameIdx,
635 const TargetRegisterClass *RC) const {
636 const TargetRegisterClass *RC,
637 const TargetRegisterInfo *TRI) const {
636638 MachineFunction &MF = *MBB.getParent();
637639 SmallVector NewMIs;
638640 DebugLoc DL;
118118 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
119119 MachineBasicBlock::iterator MBBI,
120120 unsigned SrcReg, bool isKill, int FrameIndex,
121 const TargetRegisterClass *RC) const;
121 const TargetRegisterClass *RC,
122 const TargetRegisterInfo *TRI) const;
122123
123124 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
124125 MachineBasicBlock::iterator MBBI,
125126 unsigned DestReg, int FrameIndex,
126 const TargetRegisterClass *RC) const;
127 const TargetRegisterClass *RC,
128 const TargetRegisterInfo *TRI) const;
127129
128130 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
129131 int FrameIx,
147147 void SparcInstrInfo::
148148 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
149149 unsigned SrcReg, bool isKill, int FI,
150 const TargetRegisterClass *RC) const {
150 const TargetRegisterClass *RC,
151 const TargetRegisterInfo *TRI) const {
151152 DebugLoc DL;
152153 if (I != MBB.end()) DL = I->getDebugLoc();
153154
168169 void SparcInstrInfo::
169170 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
170171 unsigned DestReg, int FI,
171 const TargetRegisterClass *RC) const {
172 const TargetRegisterClass *RC,
173 const TargetRegisterInfo *TRI) const {
172174 DebugLoc DL;
173175 if (I != MBB.end()) DL = I->getDebugLoc();
174176
7878 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
7979 MachineBasicBlock::iterator MBBI,
8080 unsigned SrcReg, bool isKill, int FrameIndex,
81 const TargetRegisterClass *RC) const;
81 const TargetRegisterClass *RC,
82 const TargetRegisterInfo *TRI) const;
8283
8384 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
8485 MachineBasicBlock::iterator MBBI,
8586 unsigned DestReg, int FrameIndex,
86 const TargetRegisterClass *RC) const;
87 const TargetRegisterClass *RC,
88 const TargetRegisterInfo *TRI) const;
8789
8890 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
8991 MachineInstr* MI,
6060 void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
6161 MachineBasicBlock::iterator MI,
6262 unsigned SrcReg, bool isKill, int FrameIdx,
63 const TargetRegisterClass *RC) const {
63 const TargetRegisterClass *RC,
64 const TargetRegisterInfo *TRI) const {
6465 DebugLoc DL;
6566 if (MI != MBB.end()) DL = MI->getDebugLoc();
6667
8990 void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
9091 MachineBasicBlock::iterator MI,
9192 unsigned DestReg, int FrameIdx,
92 const TargetRegisterClass *RC) const{
93 const TargetRegisterClass *RC,
94 const TargetRegisterInfo *TRI) const{
9395 DebugLoc DL;
9496 if (MI != MBB.end()) DL = MI->getDebugLoc();
9597
332334 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
333335 if (RegClass == &SystemZ::FP64RegClass) {
334336 MBB.addLiveIn(Reg);
335 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RegClass);
337 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), RegClass,
338 &RI);
336339 }
337340 }
338341
358361 unsigned Reg = CSI[i].getReg();
359362 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
360363 if (RegClass == &SystemZ::FP64RegClass)
361 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
364 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass, &RI);
362365 }
363366
364367 // Restore GP registers
7474 MachineBasicBlock::iterator MI,
7575 unsigned SrcReg, bool isKill,
7676 int FrameIndex,
77 const TargetRegisterClass *RC) const;
77 const TargetRegisterClass *RC,
78 const TargetRegisterInfo *TRI) const;
7879 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
7980 MachineBasicBlock::iterator MI,
8081 unsigned DestReg, int FrameIdx,
81 const TargetRegisterClass *RC) const;
82 const TargetRegisterClass *RC,
83 const TargetRegisterInfo *TRI) const;
8284
8385 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
8486 MachineBasicBlock::iterator MI,
21322132 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
21332133 MachineBasicBlock::iterator MI,
21342134 unsigned SrcReg, bool isKill, int FrameIdx,
2135 const TargetRegisterClass *RC) const {
2135 const TargetRegisterClass *RC,
2136 const TargetRegisterInfo *TRI) const {
21362137 const MachineFunction &MF = *MBB.getParent();
21372138 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
21382139 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
22292230 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
22302231 MachineBasicBlock::iterator MI,
22312232 unsigned DestReg, int FrameIdx,
2232 const TargetRegisterClass *RC) const{
2233 const TargetRegisterClass *RC,
2234 const TargetRegisterInfo *TRI) const {
22332235 const MachineFunction &MF = *MBB.getParent();
22342236 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
22352237 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
22832285 CalleeFrameSize += SlotSize;
22842286 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
22852287 } else {
2286 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2288 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass,
2289 &RI);
22872290 }
22882291 }
22892292
23132316 if (RegClass != &X86::VR128RegClass && !isWin64) {
23142317 BuildMI(MBB, MI, DL, get(Opc), Reg);
23152318 } else {
2316 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2319 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass, &RI);
23172320 }
23182321 }
23192322 return true;
593593 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
594594 MachineBasicBlock::iterator MI,
595595 unsigned SrcReg, bool isKill, int FrameIndex,
596 const TargetRegisterClass *RC) const;
596 const TargetRegisterClass *RC,
597 const TargetRegisterInfo *TRI) const;
597598
598599 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
599600 SmallVectorImpl &Addr,
605606 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
606607 MachineBasicBlock::iterator MI,
607608 unsigned DestReg, int FrameIndex,
608 const TargetRegisterClass *RC) const;
609 const TargetRegisterClass *RC,
610 const TargetRegisterInfo *TRI) const;
609611
610612 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
611613 SmallVectorImpl &Addr,
394394 MachineBasicBlock::iterator I,
395395 unsigned SrcReg, bool isKill,
396396 int FrameIndex,
397 const TargetRegisterClass *RC) const
397 const TargetRegisterClass *RC,
398 const TargetRegisterInfo *TRI) const
398399 {
399400 DebugLoc DL;
400401 if (I != MBB.end()) DL = I->getDebugLoc();
407408 void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
408409 MachineBasicBlock::iterator I,
409410 unsigned DestReg, int FrameIndex,
410 const TargetRegisterClass *RC) const
411 const TargetRegisterClass *RC,
412 const TargetRegisterInfo *TRI) const
411413 {
412414 DebugLoc DL;
413415 if (I != MBB.end()) DL = I->getDebugLoc();
436438 MBB.addLiveIn(it->getReg());
437439
438440 storeRegToStackSlot(MBB, MI, it->getReg(), true,
439 it->getFrameIdx(), it->getRegClass());
441 it->getFrameIdx(), it->getRegClass(), &RI);
440442 if (emitFrameMoves) {
441443 MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol();
442444 BuildMI(MBB, MI, DL, get(XCore::DBG_LABEL)).addSym(SaveLabel);
459461
460462 loadRegFromStackSlot(MBB, MI, it->getReg(),
461463 it->getFrameIdx(),
462 it->getRegClass());
464 it->getRegClass(), &RI);
463465 assert(MI != MBB.begin() &&
464466 "loadRegFromStackSlot didn't insert any code!");
465467 // Insert in reverse order. loadRegFromStackSlot can insert multiple
7171 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
7272 MachineBasicBlock::iterator MI,
7373 unsigned SrcReg, bool isKill, int FrameIndex,
74 const TargetRegisterClass *RC) const;
74 const TargetRegisterClass *RC,
75 const TargetRegisterInfo *TRI) const;
7576
7677 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
7778 MachineBasicBlock::iterator MI,
7879 unsigned DestReg, int FrameIndex,
79 const TargetRegisterClass *RC) const;
80 const TargetRegisterClass *RC,
81 const TargetRegisterInfo *TRI) const;
8082
8183 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
8284 MachineBasicBlock::iterator MI,