llvm.org GIT mirror llvm / 744b3a5
Remove TargetInstrInfo::copyRegToReg entirely. Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no longer a default implementation forwarding to copyRegToReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 10 years ago
6 changed file(s) with 9 addition(s) and 41 deletion(s). Raw diff Collapse all Expand all
13091309 a direct store to a stack slot, return the register number of the
13101310 destination and the FrameIndex of the stack slot.
13111311
1312
  • copyRegToReg — Copy values between a pair of registers.
  • 1312
  • copyPhysReg — Copy values between a pair of physical
  • 1313 registers.
    13131314
    13141315
  • storeRegToStackSlot — Store a register value to a stack
  • 13151316 slot.
    356356 virtual void copyPhysReg(MachineBasicBlock &MBB,
    357357 MachineBasicBlock::iterator MI, DebugLoc DL,
    358358 unsigned DestReg, unsigned SrcReg,
    359 bool KillSrc) const =0;
    359 bool KillSrc) const {
    360 assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!");
    361 }
    360362
    361363 /// storeRegToStackSlot - Store the specified register of the given register
    362364 /// class to the specified stack frame index. The store instruction is to be
    647649
    648650 virtual ScheduleHazardRecognizer *
    649651 CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const;
    650 virtual void copyPhysReg(MachineBasicBlock &MBB,
    651 MachineBasicBlock::iterator MI, DebugLoc DL,
    652 unsigned DestReg, unsigned SrcReg,
    653 bool KillSrc) const;
    654 /// copyRegToReg - Legacy hook going away soon. Targets should implement
    655 /// copyPhysReg instead.
    656 virtual bool copyRegToReg(MachineBasicBlock &MBB,
    657 MachineBasicBlock::iterator MI,
    658 unsigned DestReg, unsigned SrcReg,
    659 const TargetRegisterClass *DestRC,
    660 const TargetRegisterClass *SrcRC,
    661 DebugLoc DL) const {
    662 assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!");
    663 return false;
    664 }
    665
    666652 };
    667653
    668654 } // End llvm namespace
    6161 /// used between instruction selection and MachineInstr creation, before
    6262 /// virtual registers have been created for all the instructions, and it's
    6363 /// only needed in cases where the register classes implied by the
    64 /// instructions are insufficient. The actual MachineInstrs to perform
    65 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
    64 /// instructions are insufficient. It is emitted as a COPY MachineInstr.
    6665 COPY_TO_REGCLASS = 10,
    6766
    6867 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
    437437 CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const {
    438438 return (ScheduleHazardRecognizer *)new PostRAHazardRecognizer(II);
    439439 }
    440
    441 // Default implementation of copyPhysReg using copyRegToReg.
    442 void TargetInstrInfoImpl::copyPhysReg(MachineBasicBlock &MBB,
    443 MachineBasicBlock::iterator MI,
    444 DebugLoc DL,
    445 unsigned DestReg, unsigned SrcReg,
    446 bool KillSrc) const {
    447 assert(TargetRegisterInfo::isPhysicalRegister(DestReg));
    448 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg));
    449 const TargetRegisterInfo *TRI = MBB.getParent()->getTarget().getRegisterInfo();
    450 const TargetRegisterClass *DRC = TRI->getPhysicalRegisterRegClass(DestReg);
    451 const TargetRegisterClass *SRC = TRI->getPhysicalRegisterRegClass(SrcReg);
    452 if (!copyRegToReg(MBB, MI, DestReg, SrcReg, DRC, SRC, DL))
    453 llvm_unreachable("Cannot emit physreg copy instruction");
    454 if (KillSrc)
    455 llvm::prior(MI)->addRegisterKilled(SrcReg, TRI, true);
    456 }
    0 ; RUN: llc < %s -march=bfin
    11
    22 ; This test tries to use a JustCC register as a data operand for MOVEcc. It
    3 ; calls copyRegToReg(JustCC -> DP), failing because JustCC can only be copied to
    4 ; D. The proper solution would be to restrict the virtual register to D only.
    3 ; copies (JustCC -> DP), failing because JustCC can only be copied to D.
    4 ; The proper solution would be to restrict the virtual register to D only.
    55
    66 define i32 @main() {
    77 entry:
    8282 // the pattern.
    8383 // 6. Address expressions should become first-class entities.
    8484
    85 // Simple copy instruction. isMoveInstr could easily be inferred from this,
    86 // as could TargetRegisterInfo::copyRegToReg.
    85 // Simple copy instruction.
    8786 def MOV8rr : Inst<(ops R8:$dst, R8:$src),
    8887 "mov $dst, $src", 0x88, MRMDestReg,
    8988 [(set R8:$dst, R8:$src)]>;