llvm.org GIT mirror llvm / 74472b4
Refactor away tSpill and tRestore pseudos in ARM backend. The tSpill and tRestore instructions are just copies of the tSTRspi and tLDRspi instructions, respectively. Just use those directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134092 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 9 years ago
6 changed file(s) with 9 addition(s) and 39 deletion(s). Raw diff Collapse all Expand all
791791 break;
792792 case ARM::STRi12:
793793 case ARM::t2STRi12:
794 case ARM::tSpill:
794 case ARM::tSTRspi:
795795 case ARM::VSTRD:
796796 case ARM::VSTRS:
797797 if (MI->getOperand(1).isFI() &&
926926 break;
927927 case ARM::LDRi12:
928928 case ARM::t2LDRi12:
929 case ARM::tRestore:
929 case ARM::tLDRspi:
930930 case ARM::VLDRD:
931931 case ARM::VLDRS:
932932 if (MI->getOperand(1).isFI() &&
685685 let Inst{7-0} = addr;
686686 }
687687
688 // Special instruction for restore. It cannot clobber condition register
689 // when it's expanded by eliminateCallFramePseudoInstr().
690 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
691 // FIXME: Pseudo for tLDRspi
692 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
693 "ldr", "\t$dst, $addr", []>,
694 T1LdStSP<{1,?,?}> {
695 bits<3> Rt;
696 bits<8> addr;
697 let Inst{10-8} = Rt;
698 let Inst{7-0} = addr;
699 }
700
701688 // Load tconstpool
702689 // FIXME: Use ldr.n to work around a Darwin assembler bug.
703690 let canFoldAsLoad = 1, isReMaterializable = 1 in
748735 "str", "\t$Rt, $addr",
749736 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
750737 T1LdStSP<{0,?,?}> {
751 bits<3> Rt;
752 bits<8> addr;
753 let Inst{10-8} = Rt;
754 let Inst{7-0} = addr;
755 }
756
757 let mayStore = 1, neverHasSideEffects = 1 in
758 // Special instruction for spill. It cannot clobber condition register when it's
759 // expanded by eliminateCallFramePseudoInstr().
760 // FIXME: Pseudo for tSTRspi
761 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
762 "str", "\t$src, $addr", []>,
763 T1LdStSP<{0,?,?}> {
764738 bits<3> Rt;
765739 bits<8> addr;
766740 let Inst{10-8} = Rt;
176176 }
177177
178178 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
179 if (MI->getOpcode() == ARM::tRestore &&
179 if (MI->getOpcode() == ARM::tLDRspi &&
180180 MI->getOperand(1).isFI() &&
181181 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
182182 return true;
7474 MachineMemOperand::MOStore,
7575 MFI.getObjectSize(FI),
7676 MFI.getObjectAlignment(FI));
77 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
77 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
7878 .addReg(SrcReg, getKillRegState(isKill))
7979 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
8080 }
103103 MachineMemOperand::MOLoad,
104104 MFI.getObjectSize(FI),
105105 MFI.getObjectAlignment(FI));
106 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
106 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
107107 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
108108 }
109109 }
376376 static unsigned convertToNonSPOpcode(unsigned Opcode) {
377377 switch (Opcode) {
378378 case ARM::tLDRspi:
379 case ARM::tRestore: // FIXME: Should this opcode be here?
380379 return ARM::tLDRi;
381380
382381 case ARM::tSTRspi:
383 case ARM::tSpill: // FIXME: Should this opcode be here?
384382 return ARM::tSTRi;
385383 }
386384
523521
524522 // If this is a thumb spill / restore, we will be using a constpool load to
525523 // materialize the offset.
526 if (Opcode == ARM::tRestore || Opcode == ARM::tSpill) {
524 if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
527525 ImmOp.ChangeToImmediate(0);
528526 } else {
529527 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
663661 // Use the destination register to materialize sp + offset.
664662 unsigned TmpReg = MI.getOperand(0).getReg();
665663 bool UseRR = false;
666 if (Opcode == ARM::tRestore) {
664 if (Opcode == ARM::tLDRspi) {
667665 if (FrameReg == ARM::SP)
668666 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg,
669667 Offset, false, TII, *this);
686684 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
687685 bool UseRR = false;
688686
689 if (Opcode == ARM::tSpill) {
687 if (Opcode == ARM::tSTRspi) {
690688 if (FrameReg == ARM::SP)
691689 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
692690 Offset, false, TII, *this);
16661666 // tPOP_RET/t2LDMIA_RET conflict with tPOP/t2LDM (ditto)
16671667 // tMOVCCi conflicts with tMOVi8
16681668 // tMOVCCr conflicts with tMOVgpr2gpr
1669 // tSpill conflicts with tSTRspi
16701669 // tLDRcp conflicts with tLDRspi
1671 // tRestore conflicts with tLDRspi
16721670 // t2MOVCCi16 conflicts with tMOVi16
16731671 if (Name == "tBfar" ||
16741672 Name == "tPOP_RET" || Name == "t2LDMIA_RET" ||
16751673 Name == "tMOVCCi" || Name == "tMOVCCr" ||
1676 Name == "tSpill" || Name == "tLDRcp" || Name == "tRestore" ||
1674 Name == "tLDRcp" ||
16771675 Name == "t2MOVCCi16")
16781676 return false;
16791677 }