llvm.org GIT mirror llvm / 7417b76
Add 'isCodeGenOnly' bit to Instruction .td records. - Used to mark fake instructions which don't correspond to an actual machine instruction (or are duplicates of a real instruction). This is to be used for "special cases" in the .td files, which should be ignored by things like the assembler and disassembler. We still need a good solution to handle pervasive duplication, like with the Int_ instructions. - Set the bit on fake "mov 0" style instructions, which allows turning an assembler matcher warning into a hard error. - -2 FIXMEs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78731 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Dunbar 10 years ago
5 changed file(s) with 32 addition(s) and 29 deletion(s). Raw diff Collapse all Expand all
220220 bit mayHaveSideEffects = 0;
221221 bit neverHasSideEffects = 0;
222222
223 // Is this instruction a "real" instruction (with a distinct machine
224 // encoding), or is it a pseudo instruction used for codegen modeling
225 // purposes.
226 bit isCodeGenOnly = 0;
227
223228 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
224229
225230 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
385390 bit isLittleEndianEncoding = 0;
386391 }
387392
388 // Standard Instructions.
393 // Standard Pseudo Instructions.
394 let isCodeGenOnly = 1 in {
389395 def PHI : Instruction {
390396 let OutOperandList = (ops);
391397 let InOperandList = (ops variable_ops);
464470 let Namespace = "TargetInstrInfo";
465471 let neverHasSideEffects = 1;
466472 let isAsCheapAsAMove = 1;
473 }
467474 }
468475
469476 //===----------------------------------------------------------------------===//
31653165
31663166 // Alias instructions that map movr0 to xor.
31673167 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3168 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3168 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3169 isCodeGenOnly = 1 in {
31693170 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
31703171 "xor{b}\t$dst, $dst",
31713172 [(set GR8:$dst, 0)]>;
515515 //===----------------------------------------------------------------------===//
516516
517517 // Alias instructions that map zero vector to pxor.
518 let isReMaterializable = 1 in {
518 let isReMaterializable = 1, isCodeGenOnly = 1 in {
519519 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
520520 "pxor\t$dst, $dst",
521521 [(set VR64:$dst, (v2i32 immAllZerosV))]>;
471471 // that start with 'Fs'.
472472
473473 // Alias instructions that map fld0 to pxor for sse.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
475475 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
476476 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
477477 Requires<[HasSSE1]>, TB, OpSize;
991991 // Alias instructions that map zero vector to pxor / xorp* for sse.
992992 // We set canFoldAsLoad because this can be converted to a constant-pool
993993 // load of an all-zeros value if folding it would be beneficial.
994 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
994 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
995 isCodeGenOnly = 1 in
995996 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
996997 "xorps\t$dst, $dst",
997998 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
12071208 // that start with 'Fs'.
12081209
12091210 // Alias instructions that map fld0 to pxor for sse.
1210 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1211 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1 in
12111212 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
12121213 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
12131214 Requires<[HasSSE2]>, TB, OpSize;
22442245 // Alias instructions that map zero vector to pxor / xorp* for sse.
22452246 // We set canFoldAsLoad because this can be converted to a constant-pool
22462247 // load of an all-ones value if folding it would be beneficial.
2247 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
2248 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2249 isCodeGenOnly = 1 in
22482250 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
22492251 "pcmpeqd\t$dst, $dst",
22502252 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
209209 static bool IsAssemblerInstruction(const StringRef &Name,
210210 const CodeGenInstruction &CGI,
211211 const SmallVectorImpl &Tokens) {
212 // Ignore psuedo ops.
212 // Ignore "codegen only" instructions.
213 if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
214 return false;
215
216 // Ignore pseudo ops.
213217 //
214 // FIXME: This is a hack.
218 // FIXME: This is a hack; can we convert these instructions to set the
219 // "codegen only" bit instead?
215220 if (const RecordVal *Form = CGI.TheDef->getValue("Form"))
216221 if (Form->getValue()->getAsString() == "Pseudo")
217222 return false;
218
219 // Ignore "PHI" node.
220 //
221 // FIXME: This is also a hack.
222 if (Name == "PHI")
223 return false;
224223
225224 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases.
226225 //
244243 //
245244 // FIXME: Is this true?
246245 //
247 // Also, we ignore instructions which reference the operand multiple times;
248 // this implies a constraint we would not currently honor. These are
249 // currently always fake instructions for simplifying codegen.
250 //
251 // FIXME: Encode this assumption in the .td, so we can error out here.
246 // Also, check for instructions which reference the operand multiple times;
247 // this implies a constraint we would not honor.
252248 std::set OperandNames;
253249 for (unsigned i = 1, e = Tokens.size(); i < e; ++i) {
254250 if (Tokens[i][0] == '$' &&
257253 DEBUG({
258254 errs() << "warning: '" << Name << "': "
259255 << "ignoring instruction; operand with attribute '"
260 << Tokens[i] << "', \n";
261 });
262 return false;
263 }
264
265 if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) {
266 DEBUG({
267 errs() << "warning: '" << Name << "': "
268 << "ignoring instruction; tied operand '"
269256 << Tokens[i] << "'\n";
270257 });
271258 return false;
259 }
260
261 if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) {
262 std::string Err = "'" + Name.str() + "': " +
263 "invalid assembler instruction; tied operand '" + Tokens[i].str() + "'";
264 throw TGError(CGI.TheDef->getLoc(), Err);
272265 }
273266 }
274267