llvm.org GIT mirror llvm / 73f50d9
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 8 years ago
71 changed file(s) with 298 addition(s) and 259 deletion(s). Raw diff Collapse all Expand all
2424 // Defines symbolic names for ARM registers. This defines a mapping from
2525 // register name to register number.
2626 //
27 #include "ARMGenRegisterNames.inc"
27 #define GET_REGINFO_ENUM
28 #include "ARMGenRegisterInfo.inc"
2829
2930 // Defines symbolic names for the ARM instructions.
3031 //
3838 #include "llvm/ADT/BitVector.h"
3939 #include "llvm/ADT/SmallVector.h"
4040 #include "llvm/Support/CommandLine.h"
41 #include "ARMGenRegisterDesc.inc"
41
42 #define GET_REGINFO_MC_DESC
43 #define GET_REGINFO_TARGET_DESC
4244 #include "ARMGenRegisterInfo.inc"
4345
4446 using namespace llvm;
1515
1616 #include "ARM.h"
1717 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "ARMGenRegisterInfo.h.inc"
18
19 #define GET_REGINFO_HEADER
20 #include "ARMGenRegisterInfo.inc"
1921
2022 namespace llvm {
2123 class ARMSubtarget;
0 set(LLVM_TARGET_DEFINITIONS ARM.td)
11
2 tablegen(ARMGenRegisterNames.inc -gen-register-enums)
3 tablegen(ARMGenRegisterDesc.inc -gen-register-desc)
4 tablegen(ARMGenRegisterInfo.h.inc -gen-register-info-header)
52 tablegen(ARMGenRegisterInfo.inc -gen-register-info)
63 tablegen(ARMGenInstrNames.inc -gen-instr-enums)
74 tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
1111 TARGET = ARM
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \
15 ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \
14 BUILT_SOURCES = ARMGenRegisterInfo.inc \
1615 ARMGenInstrNames.inc ARMGenInstrInfo.inc \
1716 ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
1817 ARMGenDAGISel.inc ARMGenSubtarget.inc \
4343 // Defines symbolic names for Alpha registers. This defines a mapping from
4444 // register name to register number.
4545 //
46 #include "AlphaGenRegisterNames.inc"
46
47 #define GET_REGINFO_ENUM
48 #include "AlphaGenRegisterInfo.inc"
4749
4850 // Defines symbolic names for the Alpha instructions.
4951 //
3232 #include "llvm/ADT/BitVector.h"
3333 #include "llvm/ADT/STLExtras.h"
3434 #include
35 #include "AlphaGenRegisterDesc.inc"
35
36 #define GET_REGINFO_MC_DESC
37 #define GET_REGINFO_TARGET_DESC
3638 #include "AlphaGenRegisterInfo.inc"
39
3740 using namespace llvm;
3841
3942 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
1414 #define ALPHAREGISTERINFO_H
1515
1616 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "AlphaGenRegisterInfo.h.inc"
17
18 #define GET_REGINFO_HEADER
19 #include "AlphaGenRegisterInfo.inc"
1820
1921 namespace llvm {
2022
0 set(LLVM_TARGET_DEFINITIONS Alpha.td)
11
2 tablegen(AlphaGenRegisterNames.inc -gen-register-enums)
3 tablegen(AlphaGenRegisterDesc.inc -gen-register-desc)
4 tablegen(AlphaGenRegisterInfo.h.inc -gen-register-info-header)
52 tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
63 tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
74 tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
1111 TARGET = Alpha
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = AlphaGenRegisterNames.inc AlphaGenRegisterDesc.inc \
15 AlphaGenRegisterInfo.h.inc AlphaGenRegisterInfo.inc \
14 BUILT_SOURCES = AlphaGenRegisterInfo.inc \
1615 AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \
1716 AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
1817 AlphaGenCallingConv.inc AlphaGenSubtarget.inc
2929
3030 // Defines symbolic names for Blackfin registers. This defines a mapping from
3131 // register name to register number.
32 #include "BlackfinGenRegisterNames.inc"
32 #define GET_REGINFO_ENUM
33 #include "BlackfinGenRegisterInfo.inc"
3334
3435 // Defines symbolic names for the Blackfin instructions.
3536 #include "BlackfinGenInstrNames.inc"
2828 #include "llvm/Type.h"
2929 #include "llvm/ADT/BitVector.h"
3030 #include "llvm/ADT/STLExtras.h"
31 #include "BlackfinGenRegisterDesc.inc"
31
32 #define GET_REGINFO_MC_DESC
33 #define GET_REGINFO_TARGET_DESC
3234 #include "BlackfinGenRegisterInfo.inc"
35
3336 using namespace llvm;
3437
3538 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
1515 #define BLACKFINREGISTERINFO_H
1616
1717 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "BlackfinGenRegisterInfo.h.inc"
18
19 #define GET_REGINFO_HEADER
20 #include "BlackfinGenRegisterInfo.inc"
1921
2022 namespace llvm {
2123
0 set(LLVM_TARGET_DEFINITIONS Blackfin.td)
11
2 tablegen(BlackfinGenRegisterNames.inc -gen-register-enums)
3 tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc)
4 tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header)
52 tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
63 tablegen(BlackfinGenInstrNames.inc -gen-instr-enums)
74 tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc)
1111 TARGET = Blackfin
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \
15 BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \
16 BlackfinGenInstrNames.inc \
14 BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \
1715 BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
1816 BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
1917 BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
0 set(LLVM_TARGET_DEFINITIONS SPU.td)
11
22 tablegen(SPUGenInstrNames.inc -gen-instr-enums)
3 tablegen(SPUGenRegisterNames.inc -gen-register-enums)
43 tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
54 tablegen(SPUGenCodeEmitter.inc -gen-emitter)
6 tablegen(SPUGenRegisterDesc.inc -gen-register-desc)
7 tablegen(SPUGenRegisterInfo.h.inc -gen-register-info-header)
85 tablegen(SPUGenRegisterInfo.inc -gen-register-info)
96 tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
107 tablegen(SPUGenDAGISel.inc -gen-dag-isel)
99 LEVEL = ../../..
1010 LIBRARYNAME = LLVMCellSPUCodeGen
1111 TARGET = SPU
12 BUILT_SOURCES = SPUGenInstrNames.inc \
12 BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterInfo.inc \
1313 SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
14 SPUGenRegisterNames.inc SPUGenRegisterDesc.inc \
15 SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \
1614 SPUGenInstrInfo.inc SPUGenDAGISel.inc \
1715 SPUGenSubtarget.inc SPUGenCallingConv.inc
1816
4141 #include "llvm/ADT/BitVector.h"
4242 #include "llvm/ADT/STLExtras.h"
4343 #include
44 #include "SPUGenRegisterDesc.inc"
44
45 #define GET_REGINFO_MC_DESC
46 #define GET_REGINFO_TARGET_DESC
4547 #include "SPUGenRegisterInfo.inc"
4648
4749 using namespace llvm;
1515 #define SPU_REGISTERINFO_H
1616
1717 #include "SPU.h"
18 #include "SPUGenRegisterInfo.h.inc"
18
19 #define GET_REGINFO_HEADER
20 #include "SPUGenRegisterInfo.inc"
1921
2022 namespace llvm {
2123 class SPUSubtarget;
1212 // Define symbolic names for Cell registers. This defines a mapping from
1313 // register name to register number.
1414 //
15 #include "SPUGenRegisterNames.inc"
15 #define GET_REGINFO_ENUM
16 #include "SPUGenRegisterInfo.inc"
1617
1718 #endif
0 set(LLVM_TARGET_DEFINITIONS MBlaze.td)
11
2 tablegen(MBlazeGenRegisterNames.inc -gen-register-enums)
3 tablegen(MBlazeGenRegisterDesc.inc -gen-register-desc)
42 tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header)
5 tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
63 tablegen(MBlazeGenInstrNames.inc -gen-instr-enums)
74 tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc)
85 tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
3838
3939 // Defines symbolic names for MBlaze registers. This defines a mapping from
4040 // register name to register number.
41 #include "MBlazeGenRegisterNames.inc"
41 #define GET_REGINFO_ENUM
42 #include "MBlazeGenRegisterInfo.inc"
4243
4344 // Defines symbolic names for the MBlaze instructions.
4445 #include "MBlazeGenInstrNames.inc"
3535 #include "llvm/Support/raw_ostream.h"
3636 #include "llvm/ADT/BitVector.h"
3737 #include "llvm/ADT/STLExtras.h"
38 #include "MBlazeGenRegisterDesc.inc"
38
39 #define GET_REGINFO_MC_DESC
40 #define GET_REGINFO_TARGET_DESC
3941 #include "MBlazeGenRegisterInfo.inc"
42
4043 using namespace llvm;
4144
4245 MBlazeRegisterInfo::
1616
1717 #include "MBlaze.h"
1818 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "MBlazeGenRegisterInfo.h.inc"
19
20 #define GET_REGINFO_HEADER
21 #include "MBlazeGenRegisterInfo.inc"
2022
2123 namespace llvm {
2224 class MBlazeSubtarget;
1010 TARGET = MBlaze
1111
1212 # Make sure that tblgen is run, first thing.
13 BUILT_SOURCES = MBlazeGenRegisterInfo.h.inc MBlazeGenRegisterNames.inc \
14 MBlazeGenRegisterInfo.inc MBlazeGenRegisterDesc.inc \
15 MBlazeGenInstrNames.inc \
13 BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \
1614 MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
1715 MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
1816 MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
0 set(LLVM_TARGET_DEFINITIONS MSP430.td)
11
2 tablegen(MSP430GenRegisterNames.inc -gen-register-enums)
3 tablegen(MSP430GenRegisterDesc.inc -gen-register-desc)
4 tablegen(MSP430GenRegisterInfo.h.inc -gen-register-info-header)
52 tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
63 tablegen(MSP430GenInstrNames.inc -gen-instr-enums)
74 tablegen(MSP430GenInstrInfo.inc -gen-instr-desc)
4646
4747 // Defines symbolic names for MSP430 registers.
4848 // This defines a mapping from register name to register number.
49 #include "MSP430GenRegisterNames.inc"
49 #define GET_REGINFO_ENUM
50 #include "MSP430GenRegisterInfo.inc"
5051
5152 // Defines symbolic names for the MSP430 instructions.
5253 #include "MSP430GenInstrNames.inc"
2424 #include "llvm/Target/TargetOptions.h"
2525 #include "llvm/ADT/BitVector.h"
2626 #include "llvm/Support/ErrorHandling.h"
27 #include "MSP430GenRegisterDesc.inc"
27
28 #define GET_REGINFO_MC_DESC
29 #define GET_REGINFO_TARGET_DESC
2830 #include "MSP430GenRegisterInfo.inc"
2931
3032 using namespace llvm;
1414 #define LLVM_TARGET_MSP430REGISTERINFO_H
1515
1616 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "MSP430GenRegisterInfo.h.inc"
17
18 #define GET_REGINFO_HEADER
19 #include "MSP430GenRegisterInfo.inc"
1820
1921 namespace llvm {
2022
1111 TARGET = MSP430
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = MSP430GenRegisterInfo.h.inc MSP430GenRegisterNames.inc \
15 MSP430GenRegisterInfo.inc MSP430GenRegisterDesc.inc \
16 MSP430GenInstrNames.inc \
14 BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \
1715 MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \
1816 MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
1917 MSP430GenSubtarget.inc
0 set(LLVM_TARGET_DEFINITIONS Mips.td)
11
2 tablegen(MipsGenRegisterNames.inc -gen-register-enums)
3 tablegen(MipsGenRegisterDesc.inc -gen-register-desc)
4 tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header)
52 tablegen(MipsGenRegisterInfo.inc -gen-register-info)
63 tablegen(MipsGenInstrNames.inc -gen-instr-enums)
74 tablegen(MipsGenInstrInfo.inc -gen-instr-desc)
1111 TARGET = Mips
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \
15 MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \
16 MipsGenInstrNames.inc \
14 BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
1715 MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
1816 MipsGenDAGISel.inc MipsGenCallingConv.inc \
1917 MipsGenSubtarget.inc
3434
3535 // Defines symbolic names for Mips registers. This defines a mapping from
3636 // register name to register number.
37 #include "MipsGenRegisterNames.inc"
37 #define GET_REGINFO_ENUM
38 #include "MipsGenRegisterInfo.inc"
3839
3940 // Defines symbolic names for the Mips instructions.
4041 #include "MipsGenInstrNames.inc"
3434 #include "llvm/Support/raw_ostream.h"
3535 #include "llvm/ADT/BitVector.h"
3636 #include "llvm/ADT/STLExtras.h"
37 #include "MipsGenRegisterDesc.inc"
37
38 #define GET_REGINFO_MC_DESC
39 #define GET_REGINFO_TARGET_DESC
3840 #include "MipsGenRegisterInfo.inc"
3941
4042 using namespace llvm;
1515
1616 #include "Mips.h"
1717 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "MipsGenRegisterInfo.h.inc"
18
19 #define GET_REGINFO_HEADER
20 #include "MipsGenRegisterInfo.inc"
1921
2022 namespace llvm {
2123 class MipsSubtarget;
44 tablegen(PTXGenDAGISel.inc -gen-dag-isel)
55 tablegen(PTXGenInstrInfo.inc -gen-instr-desc)
66 tablegen(PTXGenInstrNames.inc -gen-instr-enums)
7 tablegen(PTXGenRegisterDesc.inc -gen-register-desc)
87 tablegen(PTXGenRegisterInfo.inc -gen-register-info)
9 tablegen(PTXGenRegisterInfo.h.inc -gen-register-info-header)
10 tablegen(PTXGenRegisterNames.inc -gen-register-enums)
118 tablegen(PTXGenSubtarget.inc -gen-subtarget)
129
1310 add_llvm_target(PTXCodeGen
1616 PTXGenDAGISel.inc \
1717 PTXGenInstrInfo.inc \
1818 PTXGenInstrNames.inc \
19 PTXGenRegisterDesc.inc \
2019 PTXGenRegisterInfo.inc \
21 PTXGenRegisterInfo.h.inc \
22 PTXGenRegisterNames.inc \
2320 PTXGenSubtarget.inc
2421
2522 DIRS = TargetInfo
4646 } // namespace llvm;
4747
4848 // Defines symbolic names for PTX registers.
49 #include "PTXGenRegisterNames.inc"
49 #define GET_REGINFO_ENUM
50 #include "PTXGenRegisterInfo.inc"
5051
5152 // Defines symbolic names for the PTX instructions.
5253 #include "PTXGenInstrNames.inc"
1616 #include "llvm/Support/Debug.h"
1717 #include "llvm/Support/raw_ostream.h"
1818
19 using namespace llvm;
20
21 #include "PTXGenRegisterDesc.inc"
19 #define GET_REGINFO_MC_DESC
20 #define GET_REGINFO_TARGET_DESC
2221 #include "PTXGenRegisterInfo.inc"
2322
23 using namespace llvm;
2424
2525 PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
2626 const TargetInstrInfo &TII)
1616 #include "llvm/Support/ErrorHandling.h"
1717 #include "llvm/ADT/BitVector.h"
1818
19 #include "PTXGenRegisterInfo.h.inc"
19 #define GET_REGINFO_HEADER
20 #include "PTXGenRegisterInfo.inc"
2021
2122 namespace llvm {
2223 class PTXTargetMachine;
0 set(LLVM_TARGET_DEFINITIONS PPC.td)
11
22 tablegen(PPCGenInstrNames.inc -gen-instr-enums)
3 tablegen(PPCGenRegisterNames.inc -gen-register-enums)
43 tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
54 tablegen(PPCGenCodeEmitter.inc -gen-emitter)
65 tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
7 tablegen(PPCGenRegisterDesc.inc -gen-register-desc)
8 tablegen(PPCGenRegisterInfo.h.inc -gen-register-info-header)
96 tablegen(PPCGenRegisterInfo.inc -gen-register-info)
107 tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
118 tablegen(PPCGenDAGISel.inc -gen-dag-isel)
1111 TARGET = PPC
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
14 BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterInfo.inc \
1515 PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
16 PPCGenRegisterDesc.inc \
17 PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
1816 PPCGenInstrInfo.inc PPCGenDAGISel.inc \
1917 PPCGenSubtarget.inc PPCGenCallingConv.inc \
2018 PPCGenMCCodeEmitter.inc
8383 // Defines symbolic names for PowerPC registers. This defines a mapping from
8484 // register name to register number.
8585 //
86 #include "PPCGenRegisterNames.inc"
86 #define GET_REGINFO_ENUM
87 #include "PPCGenRegisterInfo.inc"
8788
8889 // Defines symbolic names for the PowerPC instructions.
8990 //
4242 #include "llvm/ADT/BitVector.h"
4343 #include "llvm/ADT/STLExtras.h"
4444 #include
45 #include "PPCGenRegisterDesc.inc"
45
46 #define GET_REGINFO_MC_DESC
47 #define GET_REGINFO_TARGET_DESC
4648 #include "PPCGenRegisterInfo.inc"
4749
4850 // FIXME (64-bit): Eventually enable by default.
1515 #define POWERPC32_REGISTERINFO_H
1616
1717 #include "PPC.h"
18 #include "PPCGenRegisterInfo.h.inc"
1918 #include
19
20 #define GET_REGINFO_HEADER
21 #include "PPCGenRegisterInfo.inc"
2022
2123 namespace llvm {
2224 class PPCSubtarget;
0 set(LLVM_TARGET_DEFINITIONS Sparc.td)
11
2 tablegen(SparcGenRegisterNames.inc -gen-register-enums)
3 tablegen(SparcGenRegisterDesc.inc -gen-register-desc)
4 tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header)
52 tablegen(SparcGenRegisterInfo.inc -gen-register-info)
63 tablegen(SparcGenInstrNames.inc -gen-instr-enums)
74 tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
1111 TARGET = Sparc
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \
15 SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \
16 SparcGenInstrNames.inc \
14 BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
1715 SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
1816 SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc
1917
3535 // Defines symbolic names for Sparc registers. This defines a mapping from
3636 // register name to register number.
3737 //
38 #include "SparcGenRegisterNames.inc"
38 #define GET_REGINFO_ENUM
39 #include "SparcGenRegisterInfo.inc"
3940
4041 // Defines symbolic names for the Sparc instructions.
4142 //
2222 #include "llvm/Type.h"
2323 #include "llvm/ADT/BitVector.h"
2424 #include "llvm/ADT/STLExtras.h"
25 #include "SparcGenRegisterDesc.inc"
25
26 #define GET_REGINFO_MC_DESC
27 #define GET_REGINFO_TARGET_DESC
2628 #include "SparcGenRegisterInfo.inc"
29
2730 using namespace llvm;
2831
2932 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
1414 #define SPARCREGISTERINFO_H
1515
1616 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "SparcGenRegisterInfo.h.inc"
17
18 #define GET_REGINFO_HEADER
19 #include "SparcGenRegisterInfo.inc"
1820
1921 namespace llvm {
2022
0 set(LLVM_TARGET_DEFINITIONS SystemZ.td)
11
2 tablegen(SystemZGenRegisterNames.inc -gen-register-enums)
3 tablegen(SystemZGenRegisterDesc.inc -gen-register-desc)
4 tablegen(SystemZGenRegisterInfo.h.inc -gen-register-info-header)
52 tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
63 tablegen(SystemZGenInstrNames.inc -gen-instr-enums)
74 tablegen(SystemZGenInstrInfo.inc -gen-instr-desc)
1111 TARGET = SystemZ
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \
15 SystemZGenRegisterInfo.inc SystemZGenRegisterDesc.inc \
16 SystemZGenInstrNames.inc \
14 BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \
1715 SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \
1816 SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
1917
5252
5353 // Defines symbolic names for SystemZ registers.
5454 // This defines a mapping from register name to register number.
55 #include "SystemZGenRegisterNames.inc"
55 #define GET_REGINFO_ENUM
56 #include "SystemZGenRegisterInfo.inc"
5657
5758 // Defines symbolic names for the SystemZ instructions.
5859 #include "SystemZGenInstrNames.inc"
2424 #include "llvm/Target/TargetMachine.h"
2525 #include "llvm/Target/TargetOptions.h"
2626 #include "llvm/ADT/BitVector.h"
27 #include "SystemZGenRegisterDesc.inc"
27
28 #define GET_REGINFO_MC_DESC
29 #define GET_REGINFO_TARGET_DESC
2830 #include "SystemZGenRegisterInfo.inc"
31
2932 using namespace llvm;
3033
3134 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
1414 #define SystemZREGISTERINFO_H
1515
1616 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "SystemZGenRegisterInfo.h.inc"
17
18 #define GET_REGINFO_HEADER
19 #include "SystemZGenRegisterInfo.inc"
1820
1921 namespace llvm {
2022
0 set(LLVM_TARGET_DEFINITIONS X86.td)
11
2 tablegen(X86GenRegisterNames.inc -gen-register-enums)
3 tablegen(X86GenRegisterDesc.inc -gen-register-desc)
4 tablegen(X86GenRegisterInfo.h.inc -gen-register-info-header)
52 tablegen(X86GenRegisterInfo.inc -gen-register-info)
63 tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
74 tablegen(X86GenInstrNames.inc -gen-instr-enums)
2525 #include "llvm/Support/MemoryObject.h"
2626 #include "llvm/Support/raw_ostream.h"
2727
28 #include "X86GenRegisterNames.inc"
28 #define GET_REGINFO_ENUM
29 #include "X86GenRegisterInfo.inc"
2930 #include "X86GenEDInfo.inc"
3031
3132 using namespace llvm;
2626 using namespace llvm;
2727
2828 // Include the auto-generated portion of the assembly writer.
29 #define GET_REGINFO_ENUM
30 #include "X86GenRegisterInfo.inc"
2931 #define GET_INSTRUCTION_NAME
3032 #define PRINT_ALIAS_INSTR
31 #include "X86GenRegisterNames.inc"
3233 #include "X86GenAsmWriter.inc"
33 #undef PRINT_ALIAS_INSTR
34 #undef GET_INSTRUCTION_NAME
3534
3635 X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
3736 : MCInstPrinter(MAI) {
1313 #include "X86TargetDesc.h"
1414 #include "llvm/MC/MCRegisterInfo.h"
1515 #include "llvm/Target/TargetRegistry.h"
16 #include "X86GenRegisterDesc.inc"
16
17 #define GET_REGINFO_MC_DESC
18 #include "X86GenRegisterInfo.inc"
1719 using namespace llvm;
1820
1921 MCRegisterInfo *createX86MCRegisterInfo() {
2222 // Defines symbolic names for X86 registers. This defines a mapping from
2323 // register name to register number.
2424 //
25 #include "X86GenRegisterNames.inc"
25 #define GET_REGINFO_ENUM
26 #include "X86GenRegisterInfo.inc"
2627
2728 #endif
1111 TARGET = X86
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = X86GenRegisterNames.inc X86GenRegisterDesc.inc \
15 X86GenRegisterInfo.h.inc X86GenRegisterInfo.inc \
14 BUILT_SOURCES = X86GenRegisterInfo.inc \
1615 X86GenInstrNames.inc X86GenInstrInfo.inc \
1716 X86GenAsmWriter.inc X86GenAsmMatcher.inc \
1817 X86GenAsmWriter1.inc X86GenDAGISel.inc \
3838 #include "llvm/ADT/STLExtras.h"
3939 #include "llvm/Support/ErrorHandling.h"
4040 #include "llvm/Support/CommandLine.h"
41 #include "X86GenRegisterDesc.inc"
41
42 #define GET_REGINFO_MC_DESC
43 #define GET_REGINFO_TARGET_DESC
4244 #include "X86GenRegisterInfo.inc"
45
4346 using namespace llvm;
4447
4548 cl::opt
1414 #define X86REGISTERINFO_H
1515
1616 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "X86GenRegisterInfo.h.inc"
17
18 #define GET_REGINFO_HEADER
19 #include "X86GenRegisterInfo.inc"
1820
1921 namespace llvm {
2022 class Type;
0 set(LLVM_TARGET_DEFINITIONS XCore.td)
11
2 tablegen(XCoreGenRegisterNames.inc -gen-register-enums)
3 tablegen(XCoreGenRegisterDesc.inc -gen-register-desc)
4 tablegen(XCoreGenRegisterInfo.h.inc -gen-register-info-header)
52 tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
63 tablegen(XCoreGenInstrNames.inc -gen-instr-enums)
74 tablegen(XCoreGenInstrInfo.inc -gen-instr-desc)
1111 TARGET = XCore
1212
1313 # Make sure that tblgen is run, first thing.
14 BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \
15 XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \
16 XCoreGenInstrNames.inc \
14 BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \
1715 XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \
1816 XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
1917 XCoreGenSubtarget.inc
3131 // Defines symbolic names for XCore registers. This defines a mapping from
3232 // register name to register number.
3333 //
34 #include "XCoreGenRegisterNames.inc"
34 #define GET_REGINFO_ENUM
35 #include "XCoreGenRegisterInfo.inc"
3536
3637 // Defines symbolic names for the XCore instructions.
3738 //
3131 #include "llvm/Support/Debug.h"
3232 #include "llvm/Support/ErrorHandling.h"
3333 #include "llvm/Support/raw_ostream.h"
34 #include "XCoreGenRegisterDesc.inc"
34
35 #define GET_REGINFO_MC_DESC
36 #define GET_REGINFO_TARGET_DESC
3537 #include "XCoreGenRegisterInfo.inc"
38
3639 using namespace llvm;
3740
3841 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
1414 #define XCOREREGISTERINFO_H
1515
1616 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "XCoreGenRegisterInfo.h.inc"
17
18 #define GET_REGINFO_HEADER
19 #include "XCoreGenRegisterInfo.inc"
1820
1921 namespace llvm {
2022
2424 using namespace llvm;
2525
2626 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
28 CodeGenTarget Target(Records);
29 CodeGenRegBank &Bank = Target.getRegBank();
27 void
28 RegisterInfoEmitter::runEnums(raw_ostream &OS,
29 CodeGenTarget &Target, CodeGenRegBank &Bank) {
3030 const std::vector &Registers = Bank.getRegisters();
3131
3232 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
3333
3434 EmitSourceFileHeader("Target Register Enum Values", OS);
35
36 OS << "\n#ifdef GET_REGINFO_ENUM\n";
37 OS << "#undef GET_REGINFO_ENUM\n";
38
3539 OS << "namespace llvm {\n\n";
3640
3741 if (!Namespace.empty())
6266 if (!Namespace.empty())
6367 OS << "}\n";
6468 }
69
70 const std::vector &RegisterClasses =
71 Target.getRegisterClasses();
72
73 if (!RegisterClasses.empty()) {
74 OS << "\n// Register classes\n";
75 OS << "namespace " << RegisterClasses[0].Namespace << " {\n";
76 OS << "enum {\n";
77 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
78 if (i) OS << ",\n";
79 OS << " " << RegisterClasses[i].getName() << "RegClassID";
80 OS << " = " << i;
81 }
82 OS << "\n };\n";
83 OS << "}\n";
84 }
85
6586 OS << "} // End llvm namespace \n";
87 OS << "#endif // GET_REGINFO_ENUM\n\n";
6688 }
6789
68 void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
90 void RegisterInfoEmitter::runHeader(raw_ostream &OS, CodeGenTarget &Target) {
6991 EmitSourceFileHeader("Register Information Header Fragment", OS);
70 CodeGenTarget Target(Records);
92
93 OS << "\n#ifdef GET_REGINFO_HEADER\n";
94 OS << "#undef GET_REGINFO_HEADER\n";
95
7196 const std::string &TargetName = Target.getName();
7297 std::string ClassName = TargetName + "GenRegisterInfo";
7398
99124 OS << "namespace " << RegisterClasses[0].Namespace
100125 << " { // Register classes\n";
101126
102 OS << " enum {\n";
103 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
104 if (i) OS << ",\n";
105 OS << " " << RegisterClasses[i].getName() << "RegClassID";
106 OS << " = " << i;
107 }
108 OS << "\n };\n\n";
109
110127 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
111128 const CodeGenRegisterClass &RC = RegisterClasses[i];
112129 const std::string &Name = RC.getName();
128145 OS << "} // end of namespace " << TargetName << "\n\n";
129146 }
130147 OS << "} // End llvm namespace \n";
148 OS << "#endif // GET_REGINFO_HEADER\n\n";
131149 }
132150
133151 //
134 // RegisterInfoEmitter::run - Main register file description emitter.
135 //
136 void RegisterInfoEmitter::run(raw_ostream &OS) {
137 CodeGenTarget Target(Records);
138 CodeGenRegBank &RegBank = Target.getRegBank();
139 RegBank.computeDerivedInfo();
140
141 EmitSourceFileHeader("Register Information Source Fragment", OS);
152 // runMCDesc - Print out MC register descriptions.
153 //
154 void
155 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
156 CodeGenRegBank &RegBank) {
157 EmitSourceFileHeader("MC Register Information", OS);
158
159 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
160 OS << "#undef GET_REGINFO_MC_DESC\n";
161
162 std::map Overlaps;
163 RegBank.computeOverlaps(Overlaps);
164
165 OS << "namespace llvm {\n\n";
166
167 const std::string &TargetName = Target.getName();
168 std::string ClassName = TargetName + "GenMCRegisterInfo";
169 OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
170 << " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
171 OS << "};\n";
172
173 OS << "\nnamespace {\n";
174
175 const std::vector &Regs = RegBank.getRegisters();
176
177 // Emit an overlap list for all registers.
178 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
179 const CodeGenRegister *Reg = Regs[i];
180 const CodeGenRegister::Set &O = Overlaps[Reg];
181 // Move Reg to the front so TRI::getAliasSet can share the list.
182 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
183 << getQualifiedName(Reg->TheDef) << ", ";
184 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
185 I != E; ++I)
186 if (*I != Reg)
187 OS << getQualifiedName((*I)->TheDef) << ", ";
188 OS << "0 };\n";
189 }
190
191 // Emit the empty sub-registers list
192 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
193 // Loop over all of the registers which have sub-registers, emitting the
194 // sub-registers list to memory.
195 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
196 const CodeGenRegister &Reg = *Regs[i];
197 if (Reg.getSubRegs().empty())
198 continue;
199 // getSubRegs() orders by SubRegIndex. We want a topological order.
200 SetVector SR;
201 Reg.addSubRegsPreOrder(SR);
202 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
203 for (unsigned j = 0, je = SR.size(); j != je; ++j)
204 OS << getQualifiedName(SR[j]->TheDef) << ", ";
205 OS << "0 };\n";
206 }
207
208 // Emit the empty super-registers list
209 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
210 // Loop over all of the registers which have super-registers, emitting the
211 // super-registers list to memory.
212 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
213 const CodeGenRegister &Reg = *Regs[i];
214 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
215 if (SR.empty())
216 continue;
217 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
218 for (unsigned j = 0, je = SR.size(); j != je; ++j)
219 OS << getQualifiedName(SR[j]->TheDef) << ", ";
220 OS << "0 };\n";
221 }
222
223 OS << "\n const MCRegisterDesc " << TargetName
224 << "RegDesc[] = { // Descriptors\n";
225 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
226
227 // Now that register alias and sub-registers sets have been emitted, emit the
228 // register descriptors now.
229 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
230 const CodeGenRegister &Reg = *Regs[i];
231 OS << " { \"";
232 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
233 if (!Reg.getSubRegs().empty())
234 OS << Reg.getName() << "_SubRegsSet,\t";
235 else
236 OS << "Empty_SubRegsSet,\t";
237 if (!Reg.getSuperRegs().empty())
238 OS << Reg.getName() << "_SuperRegsSet";
239 else
240 OS << "Empty_SuperRegsSet";
241 OS << " },\n";
242 }
243 OS << " };\n"; // End of register descriptors...
244
245 OS << "}\n\n"; // End of anonymous namespace...
246
247 // MCRegisterInfo initialization routine.
248 OS << "static inline void Init" << TargetName
249 << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
250 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
251 << Regs.size()+1 << ");\n}\n\n";
252
253 OS << "} // End llvm namespace \n";
254 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
255 }
256
257 //
258 // runTargetDesc - Output the target register and register file descriptions.
259 //
260 void
261 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
262 CodeGenRegBank &RegBank){
263 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
264
265 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
266 OS << "#undef GET_REGINFO_TARGET_DESC\n";
142267
143268 OS << "namespace llvm {\n\n";
144269
613738 OS << " };\n}\n\n";
614739
615740 OS << "} // End llvm namespace \n";
741 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
616742 }
617743
618 void RegisterInfoEmitter::runDesc(raw_ostream &OS) {
744 void RegisterInfoEmitter::run(raw_ostream &OS) {
619745 CodeGenTarget Target(Records);
620746 CodeGenRegBank &RegBank = Target.getRegBank();
621747 RegBank.computeDerivedInfo();
622 std::map Overlaps;
623 RegBank.computeOverlaps(Overlaps);
624
625 OS << "namespace llvm {\n\n";
626
627 const std::string &TargetName = Target.getName();
628 std::string ClassName = TargetName + "GenMCRegisterInfo";
629 OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
630 << " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
631 OS << "};\n";
632
633 OS << "\nnamespace {\n";
634
635 const std::vector &Regs = RegBank.getRegisters();
636
637 // Emit an overlap list for all registers.
638 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
639 const CodeGenRegister *Reg = Regs[i];
640 const CodeGenRegister::Set &O = Overlaps[Reg];
641 // Move Reg to the front so TRI::getAliasSet can share the list.
642 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
643 << getQualifiedName(Reg->TheDef) << ", ";
644 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
645 I != E; ++I)
646 if (*I != Reg)
647 OS << getQualifiedName((*I)->TheDef) << ", ";
648 OS << "0 };\n";
649 }
650
651 // Emit the empty sub-registers list
652 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
653 // Loop over all of the registers which have sub-registers, emitting the
654 // sub-registers list to memory.
655 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
656 const CodeGenRegister &Reg = *Regs[i];
657 if (Reg.getSubRegs().empty())
658 continue;
659 // getSubRegs() orders by SubRegIndex. We want a topological order.
660 SetVector SR;
661 Reg.addSubRegsPreOrder(SR);
662 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
663 for (unsigned j = 0, je = SR.size(); j != je; ++j)
664 OS << getQualifiedName(SR[j]->TheDef) << ", ";
665 OS << "0 };\n";
666 }
667
668 // Emit the empty super-registers list
669 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
670 // Loop over all of the registers which have super-registers, emitting the
671 // super-registers list to memory.
672 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
673 const CodeGenRegister &Reg = *Regs[i];
674 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
675 if (SR.empty())
676 continue;
677 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
678 for (unsigned j = 0, je = SR.size(); j != je; ++j)
679 OS << getQualifiedName(SR[j]->TheDef) << ", ";
680 OS << "0 };\n";
681 }
682
683 OS << "\n const MCRegisterDesc " << TargetName
684 << "RegDesc[] = { // Descriptors\n";
685 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
686
687 // Now that register alias and sub-registers sets have been emitted, emit the
688 // register descriptors now.
689 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
690 const CodeGenRegister &Reg = *Regs[i];
691 OS << " { \"";
692 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
693 if (!Reg.getSubRegs().empty())
694 OS << Reg.getName() << "_SubRegsSet,\t";
695 else
696 OS << "Empty_SubRegsSet,\t";
697 if (!Reg.getSuperRegs().empty())
698 OS << Reg.getName() << "_SuperRegsSet";
699 else
700 OS << "Empty_SuperRegsSet";
701 OS << " },\n";
702 }
703 OS << " };\n"; // End of register descriptors...
704
705 OS << "}\n\n"; // End of anonymous namespace...
706
707 // MCRegisterInfo initialization routine.
708 OS << "static inline void Init" << TargetName
709 << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
710 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
711 << Regs.size()+1 << ");\n}\n\n";
712
713 OS << "} // End llvm namespace \n";
748
749 runEnums(OS, Target, RegBank);
750 runHeader(OS, Target);
751 runMCDesc(OS, Target, RegBank);
752 runTargetDesc(OS, Target, RegBank);
714753 }
1919
2020 namespace llvm {
2121
22 class CodeGenRegBank;
23 class CodeGenTarget;
24
2225 class RegisterInfoEmitter : public TableGenBackend {
2326 RecordKeeper &Records;
2427 public:
2528 RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
2629
27 // run - Output the register file description, returning true on failure.
28 void run(raw_ostream &o);
30 // runEnums - Print out enum values for all of the registers.
31 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
2932
3033 // runHeader - Emit a header fragment for the register info emitter.
31 void runHeader(raw_ostream &o);
34 void runHeader(raw_ostream &o, CodeGenTarget &Target);
3235
33 // runEnums - Print out enum values for all of the registers.
34 void runEnums(raw_ostream &o);
36 // runMCDesc - Print out MC register descriptions.
37 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
3538
36 // runDesc - Print out register descriptions.
37 void runDesc(raw_ostream &o);
39 // runTargetDesc - Output the target register and register file descriptions.
40 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
41
42 // run - Output the register file description.
43 void run(raw_ostream &o);
3844 };
3945
4046 } // End llvm namespace
5353 enum ActionType {
5454 PrintRecords,
5555 GenEmitter,
56 GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader,
56 GenRegisterInfo,
5757 GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
5858 GenARMDecoder,
5959 GenDisassembler,
9292 "Print all records to stdout (default)"),
9393 clEnumValN(GenEmitter, "gen-emitter",
9494 "Generate machine code emitter"),
95 clEnumValN(GenRegisterEnums, "gen-register-enums",
96 "Generate enum values for registers"),
97 clEnumValN(GenRegisterDesc, "gen-register-desc",
98 "Generate register descriptions"),
9995 clEnumValN(GenRegisterInfo, "gen-register-info",
100 "Generate registers & reg-classes info"),
101 clEnumValN(GenRegisterInfoHeader, "gen-register-info-header",
102 "Generate registers & reg-classes info header"),
96 "Generate registers and register classes info"),
10397 clEnumValN(GenInstrEnums, "gen-instr-enums",
10498 "Generate enum values for instructions"),
10599 clEnumValN(GenInstrs, "gen-instr-desc",
262256 case GenEmitter:
263257 CodeEmitterGen(Records).run(Out.os());
264258 break;
265 case GenRegisterEnums:
266 RegisterInfoEmitter(Records).runEnums(Out.os());
267 break;
268 case GenRegisterDesc:
269 RegisterInfoEmitter(Records).runDesc(Out.os());
270 break;
271259 case GenRegisterInfo:
272260 RegisterInfoEmitter(Records).run(Out.os());
273 break;
274 case GenRegisterInfoHeader:
275 RegisterInfoEmitter(Records).runHeader(Out.os());
276261 break;
277262 case GenInstrEnums:
278263 InstrEnumEmitter(Records).run(Out.os());