llvm.org GIT mirror llvm / 73cf709
Remove double-def checking from MachineVerifier, so a register does not have to be killed before being redefined. These checks are usually disabled, and usually fail when enabled. We de facto allow live registers to be redefined without a kill, the corresponding assertions in RegScavenger were removed long ago. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110362 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 10 years ago
4 changed file(s) with 23 addition(s) and 97 deletion(s). Raw diff Collapse all Expand all
265265
266266 /// verify - Run the current MachineFunction through the machine code
267267 /// verifier, useful for debugger use.
268 void verify(Pass *p=NULL, bool allowDoubleDefs=false) const;
268 void verify(Pass *p=NULL) const;
269269
270270 // Provide accessors for the MachineBasicBlock list...
271271 typedef BasicBlockListType::iterator iterator;
187187
188188 /// createMachineVerifierPass - This pass verifies cenerated machine code
189189 /// instructions for correctness.
190 ///
191 /// @param allowDoubleDefs ignore double definitions of
192 /// registers. Useful before LiveVariables has run.
193 FunctionPass *createMachineVerifierPass(bool allowDoubleDefs);
190 FunctionPass *createMachineVerifierPass();
194191
195192 /// createDwarfEHPass - This pass mulches exception handling code into a form
196193 /// adapted to code generation. Required if using dwarf exception handling.
235235 }
236236
237237 static void printAndVerify(PassManagerBase &PM,
238 const char *Banner,
239 bool allowDoubleDefs = false) {
238 const char *Banner) {
240239 if (PrintMachineCode)
241240 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
242241
243242 if (VerifyMachineCode)
244 PM.add(createMachineVerifierPass(allowDoubleDefs));
243 PM.add(createMachineVerifierPass());
245244 }
246245
247246 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
338337 return true;
339338
340339 // Print the instruction selected machine code...
341 printAndVerify(PM, "After Instruction Selection",
342 /* allowDoubleDefs= */ true);
340 printAndVerify(PM, "After Instruction Selection");
343341
344342 // Optimize PHIs before DCE: removing dead PHI cycles may make more
345343 // instructions dead.
352350 // used by tail calls, where the tail calls reuse the incoming stack
353351 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
354352 PM.add(createDeadMachineInstructionElimPass());
355 printAndVerify(PM, "After codegen DCE pass",
356 /* allowDoubleDefs= */ true);
353 printAndVerify(PM, "After codegen DCE pass");
357354
358355 PM.add(createOptimizeExtsPass());
359356 if (!DisableMachineLICM)
361358 PM.add(createMachineCSEPass());
362359 if (!DisableMachineSink)
363360 PM.add(createMachineSinkingPass());
364 printAndVerify(PM, "After Machine LICM, CSE and Sinking passes",
365 /* allowDoubleDefs= */ true);
361 printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
366362 }
367363
368364 // Pre-ra tail duplication.
369365 if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
370366 PM.add(createTailDuplicatePass(true));
371 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate",
372 /* allowDoubleDefs= */ true);
367 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
373368 }
374369
375370 // Run pre-ra passes.
376371 if (addPreRegAlloc(PM, OptLevel))
377 printAndVerify(PM, "After PreRegAlloc passes",
378 /* allowDoubleDefs= */ true);
372 printAndVerify(PM, "After PreRegAlloc passes");
379373
380374 // Perform register allocation.
381375 PM.add(createRegisterAllocator(OptLevel));
4343 namespace {
4444 struct MachineVerifier {
4545
46 MachineVerifier(Pass *pass, bool allowDoubleDefs) :
46 MachineVerifier(Pass *pass) :
4747 PASS(pass),
48 allowVirtDoubleDefs(allowDoubleDefs),
49 allowPhysDoubleDefs(true),
5048 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
5149 {}
5250
5351 bool runOnMachineFunction(MachineFunction &MF);
5452
5553 Pass *const PASS;
56 const bool allowVirtDoubleDefs;
57 const bool allowPhysDoubleDefs;
58
5954 const char *const OutFileName;
6055 raw_ostream *OS;
6156 const MachineFunction *MF;
8984 // Vregs that must be live in because they are used without being
9085 // defined. Map value is the user.
9186 RegMap vregsLiveIn;
92
93 // Vregs that must be dead in because they are defined without being
94 // killed first. Map value is the defining instruction.
95 RegMap vregsDeadIn;
9687
9788 // Regs killed in MBB. They may be defined again, and will then be in both
9889 // regsKilled and regsLiveOut.
198189
199190 struct MachineVerifierPass : public MachineFunctionPass {
200191 static char ID; // Pass ID, replacement for typeid
201 bool AllowDoubleDefs;
202
203 explicit MachineVerifierPass(bool allowDoubleDefs = false)
204 : MachineFunctionPass(&ID),
205 AllowDoubleDefs(allowDoubleDefs) {}
192
193 MachineVerifierPass()
194 : MachineFunctionPass(&ID) {}
206195
207196 void getAnalysisUsage(AnalysisUsage &AU) const {
208197 AU.setPreservesAll();
210199 }
211200
212201 bool runOnMachineFunction(MachineFunction &MF) {
213 MF.verify(this, AllowDoubleDefs);
202 MF.verify(this);
214203 return false;
215204 }
216205 };
222211 MachineVer("machineverifier", "Verify generated machine code");
223212 static const PassInfo *const MachineVerifyID = &MachineVer;
224213
225 FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) {
226 return new MachineVerifierPass(allowPhysDoubleDefs);
227 }
228
229 void MachineFunction::verify(Pass *p, bool allowDoubleDefs) const {
230 MachineVerifier(p, allowDoubleDefs)
231 .runOnMachineFunction(const_cast(*this));
214 FunctionPass *llvm::createMachineVerifierPass() {
215 return new MachineVerifierPass();
216 }
217
218 void MachineFunction::verify(Pass *p) const {
219 MachineVerifier(p).runOnMachineFunction(const_cast(*this));
232220 }
233221
234222 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
669657 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
670658 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
671659 set_union(MInfo.regsKilled, regsKilled);
672 set_subtract(regsLive, regsKilled);
673 regsKilled.clear();
674
675 // Verify that both and operands refer to dead registers.
676 RegVector defs(regsDefined);
677 defs.append(regsDead.begin(), regsDead.end());
678
679 for (RegVector::const_iterator I = defs.begin(), E = defs.end();
680 I != E; ++I) {
681 if (regsLive.count(*I)) {
682 if (TargetRegisterInfo::isPhysicalRegister(*I)) {
683 if (!allowPhysDoubleDefs && !isReserved(*I) &&
684 !regsLiveInButUnused.count(*I)) {
685 report("Redefining a live physical register", MI);
686 *OS << "Register " << TRI->getName(*I)
687 << " was defined but already live.\n";
688 }
689 } else {
690 if (!allowVirtDoubleDefs) {
691 report("Redefining a live virtual register", MI);
692 *OS << "Virtual register %reg" << *I
693 << " was defined but already live.\n";
694 }
695 }
696 } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
697 !MInfo.regsKilled.count(*I)) {
698 // Virtual register defined without being killed first must be dead on
699 // entry.
700 MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
701 }
702 }
703
704 set_subtract(regsLive, regsDead); regsDead.clear();
705 set_union(regsLive, regsDefined); regsDefined.clear();
660 set_subtract(regsLive, regsKilled); regsKilled.clear();
661 set_subtract(regsLive, regsDead); regsDead.clear();
662 set_union(regsLive, regsDefined); regsDefined.clear();
706663 }
707664
708665 void
827784 continue;
828785
829786 checkPHIOps(MFI);
830
831 // Verify dead-in virtual registers.
832 if (!allowVirtDoubleDefs) {
833 for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
834 PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
835 BBInfo &PrInfo = MBBInfoMap[*PrI];
836 if (!PrInfo.reachable)
837 continue;
838
839 for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
840 E = MInfo.vregsDeadIn.end(); I != E; ++I) {
841 // DeadIn register must be in neither regsLiveOut or vregsPassed of
842 // any predecessor.
843 if (PrInfo.isLiveOut(I->first)) {
844 report("Live-in virtual register redefined", I->second);
845 *OS << "Register %reg" << I->first
846 << " was live-out from predecessor MBB #"
847 << (*PrI)->getNumber() << ".\n";
848 }
849 }
850 }
851 }
852787 }
853788
854789 // Now check LiveVariables info if available