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[AArch64] Always use the version of computeKnownBits that returns a value. NFCI. Continues the work started by @bogner in rL340594 to remove uses of the KnownBits output paramater version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349908 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 1 year, 10 months ago
3 changed file(s) with 7 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
20862086 (void)BitWidth;
20872087 assert(BitWidth == 32 || BitWidth == 64);
20882088
2089 KnownBits Known;
2090 CurDAG->computeKnownBits(Op, Known);
2089 KnownBits Known = CurDAG->computeKnownBits(Op);
20912090
20922091 // Non-zero in the sense that they're not provably zero, which is the key
20932092 // point if we want to use this value
21662165
21672166 // Compute the Known Zero for the AND as this allows us to catch more general
21682167 // cases than just looking for AND with imm.
2169 KnownBits Known;
2170 CurDAG->computeKnownBits(And, Known);
2168 KnownBits Known = CurDAG->computeKnownBits(And);
21712169
21722170 // Non-zero in the sense that they're not provably zero, which is the key
21732171 // point if we want to use this value.
23082306 // This allows to catch more general case than just looking for
23092307 // AND with imm. Indeed, simplify-demanded-bits may have removed
23102308 // the AND instruction because it proves it was useless.
2311 KnownBits Known;
2312 CurDAG->computeKnownBits(OrOpd1Val, Known);
2309 KnownBits Known = CurDAG->computeKnownBits(OrOpd1Val);
23132310
23142311 // Check if there is enough room for the second operand to appear
23152312 // in the first one
992992 break;
993993 case AArch64ISD::CSEL: {
994994 KnownBits Known2;
995 DAG.computeKnownBits(Op->getOperand(0), Known, Depth + 1);
996 DAG.computeKnownBits(Op->getOperand(1), Known2, Depth + 1);
995 Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
996 Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
997997 Known.Zero &= Known2.Zero;
998998 Known.One &= Known2.One;
999999 break;
8888 auto InVec = DAG->getConstant(0, Loc, InVecVT);
8989 auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec);
9090 auto DemandedElts = APInt(2, 3);
91 KnownBits Known;
92 DAG->computeKnownBits(Op, Known, DemandedElts);
91 KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
9392 EXPECT_TRUE(Known.isZero());
9493 }
9594
104103 auto ZeroIdx = DAG->getConstant(0, Loc, IdxVT);
105104 auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx);
106105 auto DemandedElts = APInt(3, 7);
107 KnownBits Known;
108 DAG->computeKnownBits(Op, Known, DemandedElts);
106 KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
109107 EXPECT_TRUE(Known.isZero());
110108 }
111109