llvm.org GIT mirror llvm / 73c5f80
Basic 64-bit ALU operations. SPARC v9 extends all ALU instructions to 64 bits, so we simply need to add patterns to use them for both i32 and i64 values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178527 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 7 years ago
2 changed file(s) with 59 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
132132 (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i64 32)),
133133 (ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
134134 Requires<[Is64Bit]>;
135
136
137 //===----------------------------------------------------------------------===//
138 // 64-bit Integer Arithmetic and Logic.
139 //===----------------------------------------------------------------------===//
140
141 let Predicates = [Is64Bit] in {
142
143 // Register-register instructions.
144
145 def : Pat<(and i64:$a, i64:$b), (ANDrr $a, $b)>;
146 def : Pat<(or i64:$a, i64:$b), (ORrr $a, $b)>;
147 def : Pat<(xor i64:$a, i64:$b), (XORrr $a, $b)>;
148
149 def : Pat<(and i64:$a, (not i64:$b)), (ANDNrr $a, $b)>;
150 def : Pat<(or i64:$a, (not i64:$b)), (ORNrr $a, $b)>;
151 def : Pat<(xor i64:$a, (not i64:$b)), (XNORrr $a, $b)>;
152
153 def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>;
154 def : Pat<(sub i64:$a, i64:$b), (SUBrr $a, $b)>;
155
156 // Add/sub with carry were renamed to addc/subc in SPARC v9.
157 def : Pat<(adde i64:$a, i64:$b), (ADDXrr $a, $b)>;
158 def : Pat<(sube i64:$a, i64:$b), (SUBXrr $a, $b)>;
159
160 def : Pat<(addc i64:$a, i64:$b), (ADDCCrr $a, $b)>;
161 def : Pat<(subc i64:$a, i64:$b), (SUBCCrr $a, $b)>;
162
163 // Register-immediate instructions.
164
165 def : Pat<(and i64:$a, (i64 simm13:$b)), (ANDri $a, (as_i32imm $b))>;
166 def : Pat<(or i64:$a, (i64 simm13:$b)), (ORri $a, (as_i32imm $b))>;
167 def : Pat<(xor i64:$a, (i64 simm13:$b)), (XORri $a, (as_i32imm $b))>;
168
169 def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>;
170 def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>;
171
172 } // Predicates = [Is64Bit]
6464 define i64 @ret_bigimm() {
6565 ret i64 6800754272627607872
6666 }
67
68 ; CHECK: reg_reg_alu
69 ; CHECK: add %i0, %i1, [[R0:%[goli][0-7]]]
70 ; CHECK: sub [[R0]], %i2, [[R1:%[goli][0-7]]]
71 ; CHECK: andn [[R1]], %i0, %i0
72 define i64 @reg_reg_alu(i64 %x, i64 %y, i64 %z) {
73 %a = add i64 %x, %y
74 %b = sub i64 %a, %z
75 %c = xor i64 %x, -1
76 %d = and i64 %b, %c
77 ret i64 %d
78 }
79
80 ; CHECK: reg_imm_alu
81 ; CHECK: add %i0, -5, [[R0:%[goli][0-7]]]
82 ; CHECK: xor [[R0]], 2, %i0
83 define i64 @reg_imm_alu(i64 %x, i64 %y, i64 %z) {
84 %a = add i64 %x, -5
85 %b = xor i64 %a, 2
86 ret i64 %b
87 }