llvm.org GIT mirror llvm / 73a92e6
[NFC] Fixed tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365506 91177308-0d34-0410-b5e6-96231b3b80d8 David Bolvansky 2 months ago
1 changed file(s) with 290 addition(s) and 226 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt < %s -instcombine -S | FileCheck %s
2
3 define i32 @ashr_lshr_abs(i32 %x, i32 %y) {
4 ; CHECK-LABEL: @ashr_lshr_abs(
5 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
6 ; CHECK-NEXT: ret i32 [[R]]
7 ;
8 %cmp = icmp sge i32 %x, 0
9 %l = lshr i32 %x, %y
10 %r = ashr i32 %x, %y
11 %ret = select i1 %cmp, i32 %l, i32 %r
12 ret i32 %ret
13 }
14
15 define i32 @ashr_lshr_abs_both_exact(i32 %x, i32 %y) {
16 ; CHECK-LABEL: @ashr_lshr_abs(
17 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
18 ; CHECK-NEXT: ret i32 [[R]]
19 ;
20 %cmp = icmp sge i32 %x, 0
1 ; RUN: opt < %s -instsimplify -S | FileCheck %s
2
3 define i32 @ashr_lshr(i32 %x, i32 %y) {
4 ; CHECK-LABEL: @ashr_lshr(
5 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
6 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
7 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
8 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
9 ; CHECK-NEXT: ret i32 [[RET]]
10 ;
11 %cmp = icmp sgt i32 %x, -1
12 %l = lshr i32 %x, %y
13 %r = ashr i32 %x, %y
14 %ret = select i1 %cmp, i32 %l, i32 %r
15 ret i32 %ret
16 }
17
18 define i32 @ashr_lshr_exact(i32 %x, i32 %y) {
19 ; CHECK-LABEL: @ashr_lshr_exact(
20 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
21 ; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
22 ; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
23 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
24 ; CHECK-NEXT: ret i32 [[RET]]
25 ;
26 %cmp = icmp sgt i32 %x, -1
2127 %l = lshr exact i32 %x, %y
2228 %r = ashr exact i32 %x, %y
2329 %ret = select i1 %cmp, i32 %l, i32 %r
2430 ret i32 %ret
2531 }
2632
27 define i32 @ashr_lshr_abs2(i32 %x, i32 %y) {
28 ; CHECK-LABEL: @ashr_lshr_abs2(
29 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
30 ; CHECK-NEXT: ret i32 [[R]]
31 ;
32 %cmp = icmp sgt i32 %x, -1
33 %l = lshr i32 %x, %y
34 %r = ashr i32 %x, %y
35 %ret = select i1 %cmp, i32 %l, i32 %r
36 ret i32 %ret
37 }
38
39 define <2 x i32> @ashr_lshr_abs_vec(<2 x i32> %x, <2 x i32> %y) {
40 ; CHECK-LABEL: @ashr_lshr_abs_vec(
41 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
42 ; CHECK-NEXT: ret <2 x i32> [[R]]
33 define i32 @ashr_lshr2(i32 %x, i32 %y) {
34 ; CHECK-LABEL: @ashr_lshr2(
35 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
36 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
37 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
38 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
39 ; CHECK-NEXT: ret i32 [[RET]]
40 ;
41 %cmp = icmp sgt i32 %x, -1
42 %l = lshr i32 %x, %y
43 %r = ashr i32 %x, %y
44 %ret = select i1 %cmp, i32 %l, i32 %r
45 ret i32 %ret
46 }
47
48 define <2 x i32> @ashr_lshr_vec(<2 x i32> %x, <2 x i32> %y) {
49 ; CHECK-LABEL: @ashr_lshr_vec(
50 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
51 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
52 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
53 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
54 ; CHECK-NEXT: ret <2 x i32> [[RET]]
55 ;
56 %cmp = icmp sgt <2 x i32> %x,
57 %l = lshr <2 x i32> %x, %y
58 %r = ashr <2 x i32> %x, %y
59 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
60 ret <2 x i32> %ret
61 }
62
63 define <2 x i32> @ashr_lshr_vec2(<2 x i32> %x, <2 x i32> %y) {
64 ; CHECK-LABEL: @ashr_lshr_vec2(
65 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
66 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
67 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
68 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
69 ; CHECK-NEXT: ret <2 x i32> [[RET]]
70 ;
71 %cmp = icmp sgt <2 x i32> %x,
72 %l = lshr <2 x i32> %x, %y
73 %r = ashr <2 x i32> %x, %y
74 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
75 ret <2 x i32> %ret
76 }
77
78 define <2 x i32> @ashr_lshr_vec3(<2 x i32> %x, <2 x i32> %y) {
79 ; CHECK-LABEL: @ashr_lshr_vec3(
80 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]],
81 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
82 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
83 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
84 ; CHECK-NEXT: ret <2 x i32> [[RET]]
85 ;
86 %cmp = icmp slt <2 x i32> %x,
87 %l = lshr <2 x i32> %x, %y
88 %r = ashr <2 x i32> %x, %y
89 %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
90 ret <2 x i32> %ret
91 }
92
93 define i32 @ashr_lshr_inv(i32 %x, i32 %y) {
94 ; CHECK-LABEL: @ashr_lshr_inv(
95 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
96 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
97 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
98 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
99 ; CHECK-NEXT: ret i32 [[RET]]
100 ;
101 %cmp = icmp slt i32 %x, 1
102 %l = lshr i32 %x, %y
103 %r = ashr i32 %x, %y
104 %ret = select i1 %cmp, i32 %r, i32 %l
105 ret i32 %ret
106 }
107
108 define <2 x i32> @ashr_lshr_inv_vec(<2 x i32> %x, <2 x i32> %y) {
109 ; CHECK-LABEL: @ashr_lshr_inv_vec(
110 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]],
111 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
112 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
113 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
114 ; CHECK-NEXT: ret <2 x i32> [[RET]]
115 ;
116 %cmp = icmp slt <2 x i32> %x,
117 %l = lshr <2 x i32> %x, %y
118 %r = ashr <2 x i32> %x, %y
119 %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
120 ret <2 x i32> %ret
121 }
122
123 define i32 @ashr_lshr_exact_mismatch(i32 %x, i32 %y) {
124 ; CHECK-LABEL: @ashr_lshr_exact_mismatch(
125 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
126 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
127 ; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
128 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
129 ; CHECK-NEXT: ret i32 [[RET]]
130 ;
131 %cmp = icmp sgt i32 %x, -1
132 %l = lshr i32 %x, %y
133 %r = ashr exact i32 %x, %y
134 %ret = select i1 %cmp, i32 %l, i32 %r
135 ret i32 %ret
136 }
137
138 define i32 @ashr_lshr_exact_mismatch2(i32 %x, i32 %y) {
139 ; CHECK-LABEL: @ashr_lshr_exact_mismatch2(
140 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
141 ; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
142 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
143 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
144 ; CHECK-NEXT: ret i32 [[RET]]
145 ;
146 %cmp = icmp sgt i32 %x, -1
147 %l = lshr exact i32 %x, %y
148 %r = ashr i32 %x, %y
149 %ret = select i1 %cmp, i32 %l, i32 %r
150 ret i32 %ret
151 }
152
153 ; Negative tests
154
155 define i32 @ashr_lshr_wrong(i32 %x, i32 %y) {
156 ; CHECK-LABEL: @ashr_lshr_wrong(
157 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], -1
158 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
159 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
160 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
161 ; CHECK-NEXT: ret i32 [[RET]]
162 ;
163 %cmp = icmp sge i32 %x, -1
164 %l = lshr i32 %x, %y
165 %r = ashr i32 %x, %y
166 %ret = select i1 %cmp, i32 %l, i32 %r
167 ret i32 %ret
168 }
169
170 define i32 @ashr_lshr_shift_wrong_pred(i32 %x, i32 %y, i32 %z) {
171 ; CHECK-LABEL: @ashr_lshr_shift_wrong_pred(
172 ; CHECK-NEXT: [[CMP:%.*]] = icmp sle i32 [[X:%.*]], 0
173 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
174 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
175 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
176 ; CHECK-NEXT: ret i32 [[RET]]
177 ;
178 %cmp = icmp sle i32 %x, 0
179 %l = lshr i32 %x, %y
180 %r = ashr i32 %x, %y
181 %ret = select i1 %cmp, i32 %l, i32 %r
182 ret i32 %ret
183 }
184
185 define i32 @ashr_lshr_shift_wrong_pred2(i32 %x, i32 %y, i32 %z) {
186 ; CHECK-LABEL: @ashr_lshr_shift_wrong_pred2(
187 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[Z:%.*]], 0
188 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
189 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
190 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
191 ; CHECK-NEXT: ret i32 [[RET]]
192 ;
193 %cmp = icmp sge i32 %z, 0
194 %l = lshr i32 %x, %y
195 %r = ashr i32 %x, %y
196 %ret = select i1 %cmp, i32 %l, i32 %r
197 ret i32 %ret
198 }
199
200 define i32 @ashr_lshr_wrong_operands(i32 %x, i32 %y) {
201 ; CHECK-LABEL: @ashr_lshr_wrong_operands(
202 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
203 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
204 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
205 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
206 ; CHECK-NEXT: ret i32 [[RET]]
207 ;
208 %cmp = icmp sge i32 %x, 0
209 %l = lshr i32 %x, %y
210 %r = ashr i32 %x, %y
211 %ret = select i1 %cmp, i32 %r, i32 %l
212 ret i32 %ret
213 }
214
215 define i32 @ashr_lshr_no_ashr(i32 %x, i32 %y) {
216 ; CHECK-LABEL: @ashr_lshr_no_ashr(
217 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
218 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
219 ; CHECK-NEXT: [[R:%.*]] = xor i32 [[X]], [[Y]]
220 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
221 ; CHECK-NEXT: ret i32 [[RET]]
222 ;
223 %cmp = icmp sge i32 %x, 0
224 %l = lshr i32 %x, %y
225 %r = xor i32 %x, %y
226 %ret = select i1 %cmp, i32 %l, i32 %r
227 ret i32 %ret
228 }
229
230 define i32 @ashr_lshr_shift_amt_mismatch(i32 %x, i32 %y, i32 %z) {
231 ; CHECK-LABEL: @ashr_lshr_shift_amt_mismatch(
232 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
233 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
234 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Z:%.*]]
235 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
236 ; CHECK-NEXT: ret i32 [[RET]]
237 ;
238 %cmp = icmp sge i32 %x, 0
239 %l = lshr i32 %x, %y
240 %r = ashr i32 %x, %z
241 %ret = select i1 %cmp, i32 %l, i32 %r
242 ret i32 %ret
243 }
244
245 define i32 @ashr_lshr_shift_base_mismatch(i32 %x, i32 %y, i32 %z) {
246 ; CHECK-LABEL: @ashr_lshr_shift_base_mismatch(
247 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
248 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
249 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[Z:%.*]], [[Y]]
250 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
251 ; CHECK-NEXT: ret i32 [[RET]]
252 ;
253 %cmp = icmp sge i32 %x, 0
254 %l = lshr i32 %x, %y
255 %r = ashr i32 %z, %y
256 %ret = select i1 %cmp, i32 %l, i32 %r
257 ret i32 %ret
258 }
259
260 define i32 @ashr_lshr_no_lshr(i32 %x, i32 %y) {
261 ; CHECK-LABEL: @ashr_lshr_no_lshr(
262 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge i32 [[X:%.*]], 0
263 ; CHECK-NEXT: [[L:%.*]] = add i32 [[X]], [[Y:%.*]]
264 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
265 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
266 ; CHECK-NEXT: ret i32 [[RET]]
267 ;
268 %cmp = icmp sge i32 %x, 0
269 %l = add i32 %x, %y
270 %r = ashr i32 %x, %y
271 %ret = select i1 %cmp, i32 %l, i32 %r
272 ret i32 %ret
273 }
274
275 define <2 x i32> @ashr_lshr_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
276 ; CHECK-LABEL: @ashr_lshr_vec_wrong_pred(
277 ; CHECK-NEXT: [[CMP:%.*]] = icmp sle <2 x i32> [[X:%.*]], zeroinitializer
278 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
279 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
280 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
281 ; CHECK-NEXT: ret <2 x i32> [[RET]]
282 ;
283 %cmp = icmp sle <2 x i32> %x, zeroinitializer
284 %l = lshr <2 x i32> %x, %y
285 %r = ashr <2 x i32> %x, %y
286 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
287 ret <2 x i32> %ret
288 }
289
290 define <2 x i32> @ashr_lshr_inv_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
291 ; CHECK-LABEL: @ashr_lshr_inv_vec_wrong_pred(
292 ; CHECK-NEXT: [[CMP:%.*]] = icmp sge <2 x i32> [[X:%.*]], zeroinitializer
293 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
294 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
295 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
296 ; CHECK-NEXT: ret <2 x i32> [[RET]]
43297 ;
44298 %cmp = icmp sge <2 x i32> %x, zeroinitializer
45299 %l = lshr <2 x i32> %x, %y
46300 %r = ashr <2 x i32> %x, %y
47 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
48 ret <2 x i32> %ret
49 }
50
51 define i32 @ashr_lshr_nabs2(i32 %x, i32 %y) {
52 ; CHECK-LABEL: @ashr_lshr_nabs2(
53 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
54 ; CHECK-NEXT: ret i32 [[R]]
55 ;
56 %cmp = icmp sle i32 %x, 0
57 %l = lshr i32 %x, %y
58 %r = ashr i32 %x, %y
59 %ret = select i1 %cmp, i32 %r, i32 %l
60 ret i32 %ret
61 }
62
63 define i32 @ashr_lshr_nabs(i32 %x, i32 %y) {
64 ; CHECK-LABEL: @ashr_lshr_nabs(
65 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
66 ; CHECK-NEXT: ret i32 [[R]]
67 ;
68 %cmp = icmp slt i32 %x, 1
69 %l = lshr i32 %x, %y
70 %r = ashr i32 %x, %y
71 %ret = select i1 %cmp, i32 %r, i32 %l
72 ret i32 %ret
73 }
74
75 define <2 x i32> @ashr_lshr_nabs_vec(<2 x i32> %x, <2 x i32> %y) {
76 ; CHECK-LABEL: @ashr_lshr_nabs_vec(
77 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
78 ; CHECK-NEXT: ret <2 x i32> [[R]]
79 ;
80 %cmp = icmp sle <2 x i32> %x, zeroinitializer
81 %l = lshr <2 x i32> %x, %y
82 %r = ashr <2 x i32> %x, %y
83301 %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
84302 ret <2 x i32> %ret
85303 }
86
87
88 ; Negative tests
89
90 define i32 @ashr_lshr_wrong_abs(i32 %x, i32 %y) {
91 ; CHECK-LABEL: @ashr_lshr_wrong_abs(
92 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -2
93 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
94 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
95 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
96 ; CHECK-NEXT: ret i32 [[RET]]
97 ;
98 %cmp = icmp sge i32 %x, -1
99 %l = lshr i32 %x, %y
100 %r = ashr i32 %x, %y
101 %ret = select i1 %cmp, i32 %l, i32 %r
102 ret i32 %ret
103 }
104
105 define i32 @ashr_lshr_abs_shift_wrong_pred(i32 %x, i32 %y, i32 %z) {
106 ; CHECK-LABEL: @ashr_lshr_abs_shift_wrong_pred(
107 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
108 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
109 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
110 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
111 ; CHECK-NEXT: ret i32 [[RET]]
112 ;
113 %cmp = icmp sle i32 %x, 0
114 %l = lshr i32 %x, %y
115 %r = ashr i32 %x, %y
116 %ret = select i1 %cmp, i32 %l, i32 %r
117 ret i32 %ret
118 }
119
120 define i32 @ashr_lshr_abs_shift_wrong_pred2(i32 %x, i32 %y, i32 %z) {
121 ; CHECK-LABEL: @ashr_lshr_abs_shift_wrong_pred2(
122 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[Z:%.*]], -1
123 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]]
124 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
125 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
126 ; CHECK-NEXT: ret i32 [[RET]]
127 ;
128 %cmp = icmp sge i32 %z, 0
129 %l = lshr i32 %x, %y
130 %r = ashr i32 %x, %y
131 %ret = select i1 %cmp, i32 %l, i32 %r
132 ret i32 %ret
133 }
134
135 define i32 @ashr_lshr_abs_wrong_operands(i32 %x, i32 %y) {
136 ; CHECK-LABEL: @ashr_lshr_abs_wrong_operands(
137 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
138 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
139 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
140 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
141 ; CHECK-NEXT: ret i32 [[RET]]
142 ;
143 %cmp = icmp sge i32 %x, 0
144 %l = lshr i32 %x, %y
145 %r = ashr i32 %x, %y
146 %ret = select i1 %cmp, i32 %r, i32 %l
147 ret i32 %ret
148 }
149
150 define i32 @ashr_lshr_abs_no_ashr(i32 %x, i32 %y) {
151 ; CHECK-LABEL: @ashr_lshr_abs_no_ashr(
152 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
153 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
154 ; CHECK-NEXT: [[R:%.*]] = xor i32 [[X]], [[Y]]
155 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
156 ; CHECK-NEXT: ret i32 [[RET]]
157 ;
158 %cmp = icmp sge i32 %x, 0
159 %l = lshr i32 %x, %y
160 %r = xor i32 %x, %y
161 %ret = select i1 %cmp, i32 %l, i32 %r
162 ret i32 %ret
163 }
164
165 define i32 @ashr_lshr_abs_shift_amt_mismatch(i32 %x, i32 %y, i32 %z) {
166 ; CHECK-LABEL: @ashr_lshr_abs_shift_amt_mismatch(
167 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
168 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
169 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Z:%.*]]
170 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
171 ; CHECK-NEXT: ret i32 [[RET]]
172 ;
173 %cmp = icmp sge i32 %x, 0
174 %l = lshr i32 %x, %y
175 %r = ashr i32 %x, %z
176 %ret = select i1 %cmp, i32 %l, i32 %r
177 ret i32 %ret
178 }
179
180 define i32 @ashr_lshr_abs_shift_base_mismatch(i32 %x, i32 %y, i32 %z) {
181 ; CHECK-LABEL: @ashr_lshr_abs_shift_base_mismatch(
182 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
183 ; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
184 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[Z:%.*]], [[Y]]
185 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
186 ; CHECK-NEXT: ret i32 [[RET]]
187 ;
188 %cmp = icmp sge i32 %x, 0
189 %l = lshr i32 %x, %y
190 %r = ashr i32 %z, %y
191 %ret = select i1 %cmp, i32 %l, i32 %r
192 ret i32 %ret
193 }
194
195 define i32 @ashr_lshr_abs_no_lshr(i32 %x, i32 %y) {
196 ; CHECK-LABEL: @ashr_lshr_abs_no_lshr(
197 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
198 ; CHECK-NEXT: [[L:%.*]] = add i32 [[X]], [[Y:%.*]]
199 ; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
200 ; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
201 ; CHECK-NEXT: ret i32 [[RET]]
202 ;
203 %cmp = icmp sge i32 %x, 0
204 %l = add i32 %x, %y
205 %r = ashr i32 %x, %y
206 %ret = select i1 %cmp, i32 %l, i32 %r
207 ret i32 %ret
208 }
209
210 define <2 x i32> @ashr_lshr_abs_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
211 ; CHECK-LABEL: @ashr_lshr_abs_vec_wrong_pred(
212 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]],
213 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
214 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
215 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
216 ; CHECK-NEXT: ret <2 x i32> [[RET]]
217 ;
218 %cmp = icmp sle <2 x i32> %x, zeroinitializer
219 %l = lshr <2 x i32> %x, %y
220 %r = ashr <2 x i32> %x, %y
221 %ret = select <2 x i1> %cmp, <2 x i32> %l, <2 x i32> %r
222 ret <2 x i32> %ret
223 }
224
225 define <2 x i32> @ashr_lshr_nabs_vec_wrong_pred(<2 x i32> %x, <2 x i32> %y) {
226 ; CHECK-LABEL: @ashr_lshr_nabs_vec_wrong_pred(
227 ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]],
228 ; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
229 ; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
230 ; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
231 ; CHECK-NEXT: ret <2 x i32> [[RET]]
232 ;
233 %cmp = icmp sge <2 x i32> %x, zeroinitializer
234 %l = lshr <2 x i32> %x, %y
235 %r = ashr <2 x i32> %x, %y
236 %ret = select <2 x i1> %cmp, <2 x i32> %r, <2 x i32> %l
237 ret <2 x i32> %ret
238 }
239