llvm.org GIT mirror llvm / 73675f1
AMDGPU/GlobalISel: InstrMapping for G_ZEXT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326589 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
2 changed file(s) with 51 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
321321 unsigned SrcSize = getSizeInBits(Src, MRI, *TRI);
322322 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
323323 OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize);
324 break;
325 }
326 case AMDGPU::G_ZEXT: {
327 unsigned Dst = MI.getOperand(0).getReg();
328 unsigned Src = MI.getOperand(1).getReg();
329 unsigned DstSize = getSizeInBits(Dst, MRI, *TRI);
330 unsigned SrcSize = getSizeInBits(Src, MRI, *TRI);
331 unsigned SrcBank = getRegBankID(Src, MRI, *TRI,
332 SrcSize == 1 ? AMDGPU::SGPRRegBankID :
333 AMDGPU::VGPRRegBankID);
334 unsigned DstBank = SrcBank;
335 if (SrcSize == 1) {
336 if (SrcBank == AMDGPU::SGPRRegBankID)
337 DstBank = AMDGPU::VGPRRegBankID;
338 else
339 DstBank = AMDGPU::SGPRRegBankID;
340 }
341
342 OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, DstSize);
343 OpdsMapping[1] = AMDGPU::getValueMapping(SrcBank, SrcSize);
324344 break;
325345 }
326346 case AMDGPU::G_FCMP: {
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
3
4 ---
5 name: zext_i32_to_i64_s
6 legalized: true
7
8 body: |
9 bb.0:
10 liveins: $sgpr0
11 ; CHECK-LABEL: name: zext_i32_to_i64_s
12 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
13 ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s64) = G_ZEXT [[COPY]](s32)
14 %0:_(s32) = COPY $sgpr0
15 %1:_(s64) = G_ZEXT %0
16 ...
17
18 ---
19 name: zext_i32_to_i64_v
20 legalized: true
21
22 body: |
23 bb.0:
24 liveins: $vgpr0_vgpr1
25 ; CHECK-LABEL: name: zext_i32_to_i64_v
26 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
27 ; CHECK: [[ZEXT:%[0-9]+]]:vgpr(s64) = G_ZEXT [[COPY]](s32)
28 %0:_(s32) = COPY $vgpr0
29 %1:_(s64) = G_ZEXT %0
30 ...