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[AMDGPU] Stop using MCRegisterClass::getSize() Differential Review: https://reviews.llvm.org/D24675 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284619 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 3 years ago
4 changed file(s) with 46 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
402402 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
403403 int RCID = Desc.OpInfo[OpNo].RegClass;
404404 if (RCID != -1) {
405 const MCRegisterClass &ImmRC = MRI.getRegClass(RCID);
406 if (ImmRC.getSize() == 4)
405 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
406 if (RCBits == 32)
407407 printImmediate32(Op.getImm(), O);
408 else if (ImmRC.getSize() == 8)
408 else if (RCBits == 64)
409409 printImmediate64(Op.getImm(), O);
410410 else
411411 llvm_unreachable("Invalid register class size");
423423 O << "0.0";
424424 else {
425425 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
426 const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
427
428 if (ImmRC.getSize() == 4)
426 int RCID = Desc.OpInfo[OpNo].RegClass;
427 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
428 if (RCBits == 32)
429429 printImmediate32(FloatToBits(Op.getFPImm()), O);
430 else if (ImmRC.getSize() == 8)
430 else if (RCBits == 64)
431431 printImmediate64(DoubleToBits(Op.getFPImm()), O);
432432 else
433433 llvm_unreachable("Invalid register class size");
213213
214214 // Is this operand a literal immediate?
215215 const MCOperand &Op = MI.getOperand(i);
216 if (getLitEncoding(Op, RC.getSize(), STI) != 255)
216 if (getLitEncoding(Op, AMDGPU::getRegBitWidth(RC) / 8, STI) != 255)
217217 continue;
218218
219219 // Yes! Encode it
336336 OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
337337 }
338338
339 // Avoid using MCRegisterClass::getSize, since that function will go away
340 // (move from MC* level to Target* level). Return size in bits.
341 unsigned getRegBitWidth(const MCRegisterClass &RC) {
342 switch (RC.getID()) {
343 case AMDGPU::SGPR_32RegClassID:
344 case AMDGPU::VGPR_32RegClassID:
345 case AMDGPU::VS_32RegClassID:
346 case AMDGPU::SReg_32RegClassID:
347 case AMDGPU::SReg_32_XM0RegClassID:
348 return 32;
349 case AMDGPU::SGPR_64RegClassID:
350 case AMDGPU::VS_64RegClassID:
351 case AMDGPU::SReg_64RegClassID:
352 case AMDGPU::VReg_64RegClassID:
353 return 64;
354 case AMDGPU::VReg_96RegClassID:
355 return 96;
356 case AMDGPU::SGPR_128RegClassID:
357 case AMDGPU::SReg_128RegClassID:
358 case AMDGPU::VReg_128RegClassID:
359 return 128;
360 case AMDGPU::SReg_256RegClassID:
361 case AMDGPU::VReg_256RegClassID:
362 return 256;
363 case AMDGPU::SReg_512RegClassID:
364 case AMDGPU::VReg_512RegClassID:
365 return 512;
366 default:
367 llvm_unreachable("Unexpected register class");
368 }
369 }
370
339371 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
340372 unsigned OpNo) {
341 int RCID = Desc.OpInfo[OpNo].RegClass;
342 const MCRegisterClass &RC = MRI->getRegClass(RCID);
343 return RC.getSize();
373 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
374 return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
344375 }
345376
346377 bool isInlinableLiteral64(int64_t Literal, bool IsVI) {
2323 class GlobalValue;
2424 class MCContext;
2525 class MCInstrDesc;
26 class MCRegisterClass;
2627 class MCRegisterInfo;
2728 class MCSection;
2829 class MCSubtargetInfo;
151152 /// \brief Does this opearnd support only inlinable literals?
152153 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
153154
155 /// \brief Get the size in bits of a register from the register class \p RC.
156 unsigned getRegBitWidth(const MCRegisterClass &RC);
157
154158 /// \brief Get size of register operand
155159 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
156160 unsigned OpNo);