llvm.org GIT mirror llvm / 72d58f8
AMDGPU/GlobalISel: Remove default register mapping This crashes for some opcodes, which prevents the SelectionDAG fallback from working. Patch by Tom Stellard git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326487 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
1 changed file(s) with 1 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
227227 const MachineRegisterInfo &MRI = MF.getRegInfo();
228228 SmallVector OpdsMapping(MI.getNumOperands());
229229
230 bool IsComplete = true;
231230 switch (MI.getOpcode()) {
232231 default:
233 IsComplete = false;
232 return getInvalidInstructionMapping();
234233 break;
235234 case AMDGPU::G_IMPLICIT_DEF: {
236235 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
327326 return getInstrMappingForLoad(MI);
328327 }
329328
330 if (!IsComplete) {
331 unsigned BankID = AMDGPU::SGPRRegBankID;
332
333 unsigned Size = 0;
334 for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx) {
335 // If the operand is not a register default to the size of the previous
336 // operand.
337 // FIXME: Can't we pull the types from the MachineInstr rather than the
338 // operands.
339 if (MI.getOperand(Idx).isReg())
340 Size = getSizeInBits(MI.getOperand(Idx).getReg(), MRI, *TRI);
341 OpdsMapping.push_back(AMDGPU::getValueMapping(BankID, Size));
342 }
343 }
344329 return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
345330 MI.getNumOperands());
346331 }